Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7589509 [patent_doc_number] => 07664934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Data processor decoding instruction formats using operand data' [patent_app_type] => utility [patent_app_number] => 11/706333 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 17473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/664/07664934.pdf [firstpage_image] =>[orig_patent_app_number] => 11706333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706333
Data processor decoding instruction formats using operand data Feb 14, 2007 Issued
Array ( [id] => 146584 [patent_doc_number] => 07689812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Method and system for restoring register mapper states for an out-of-order microprocessor' [patent_app_type] => utility [patent_app_number] => 11/674754 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689812.pdf [firstpage_image] =>[orig_patent_app_number] => 11674754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674754
Method and system for restoring register mapper states for an out-of-order microprocessor Feb 13, 2007 Issued
Array ( [id] => 37531 [patent_doc_number] => 07793077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Alignment and ordering of vector elements for single instruction multiple data processing' [patent_app_type] => utility [patent_app_number] => 11/702659 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 8806 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793077.pdf [firstpage_image] =>[orig_patent_app_number] => 11702659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702659
Alignment and ordering of vector elements for single instruction multiple data processing Feb 5, 2007 Issued
Array ( [id] => 5071472 [patent_doc_number] => 20070192574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Branch target buffer, a branch prediction circuit and method thereof' [patent_app_type] => utility [patent_app_number] => 11/700780 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4981 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192574.pdf [firstpage_image] =>[orig_patent_app_number] => 11700780 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700780
Branch target buffer, a branch prediction circuit and method thereof Jan 31, 2007 Abandoned
Array ( [id] => 7687820 [patent_doc_number] => 20070106878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => utility [patent_app_number] => 11/642599 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 31952 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106878.pdf [firstpage_image] =>[orig_patent_app_number] => 11642599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/642599
High-performance, superscalar-based computer system with out-of-order instruction execution Dec 20, 2006 Issued
Array ( [id] => 5369911 [patent_doc_number] => 20090307470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/093884 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 18483 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307470.pdf [firstpage_image] =>[orig_patent_app_number] => 12093884 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/093884
Multi thread processor having dynamic reconfiguration logic circuit Nov 20, 2006 Issued
Array ( [id] => 28225 [patent_doc_number] => 07797514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Scalable multi-threaded sequencing/synchronizing processor architecture' [patent_app_type] => utility [patent_app_number] => 11/560370 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2951 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797514.pdf [firstpage_image] =>[orig_patent_app_number] => 11560370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560370
Scalable multi-threaded sequencing/synchronizing processor architecture Nov 15, 2006 Issued
Array ( [id] => 4804732 [patent_doc_number] => 20080016321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Interleaved hardware multithreading processor architecture' [patent_app_type] => utility [patent_app_number] => 11/599732 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016321.pdf [firstpage_image] =>[orig_patent_app_number] => 11599732 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599732
Interleaved hardware multithreading processor architecture Nov 14, 2006 Issued
Array ( [id] => 4804701 [patent_doc_number] => 20080016290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Dynamic instruction and data updating architecture' [patent_app_type] => utility [patent_app_number] => 11/599967 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11989 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016290.pdf [firstpage_image] =>[orig_patent_app_number] => 11599967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599967
Dynamic instruction and data updating architecture Nov 14, 2006 Issued
Array ( [id] => 8667493 [patent_doc_number] => 08380966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging' [patent_app_type] => utility [patent_app_number] => 11/560344 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8592 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11560344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560344
Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging Nov 14, 2006 Issued
Array ( [id] => 8810289 [patent_doc_number] => 08447957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Coprocessor interface architecture and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/598990 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11598990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598990
Coprocessor interface architecture and methods of operating the same Nov 13, 2006 Issued
Array ( [id] => 245082 [patent_doc_number] => 07590826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Speculative data value usage' [patent_app_type] => utility [patent_app_number] => 11/593151 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3948 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590826.pdf [firstpage_image] =>[orig_patent_app_number] => 11593151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593151
Speculative data value usage Nov 5, 2006 Issued
Array ( [id] => 4966819 [patent_doc_number] => 20080109639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Execution of instructions within a data processing apparatus having a plurality of processing units' [patent_app_type] => utility [patent_app_number] => 11/592337 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5638 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109639.pdf [firstpage_image] =>[orig_patent_app_number] => 11592337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592337
Execution of instructions within a data processing apparatus having a plurality of processing units Nov 2, 2006 Issued
Array ( [id] => 4631864 [patent_doc_number] => 08010774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Breakpointing on register access events or I/O port access events' [patent_app_type] => utility [patent_app_number] => 11/592323 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4205 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010774.pdf [firstpage_image] =>[orig_patent_app_number] => 11592323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592323
Breakpointing on register access events or I/O port access events Nov 2, 2006 Issued
Array ( [id] => 5173563 [patent_doc_number] => 20070074002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Data packet arithmetic logic devices and methods' [patent_app_type] => utility [patent_app_number] => 11/591108 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8589 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074002.pdf [firstpage_image] =>[orig_patent_app_number] => 11591108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591108
Data packet arithmetic logic devices and methods Oct 30, 2006 Issued
Array ( [id] => 5081339 [patent_doc_number] => 20070124563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'PROCESSING DEVICE, METHOD OF DETERMINING INTERNAL CONFIGURATION OF PROCESSING DEVICE, AND PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/553165 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18865 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124563.pdf [firstpage_image] =>[orig_patent_app_number] => 11553165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553165
Processing device, method of determining internal configuration of processing device, and processing system Oct 25, 2006 Issued
Array ( [id] => 4905552 [patent_doc_number] => 20080114966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Determining register availability for register renaming' [patent_app_type] => utility [patent_app_number] => 11/586007 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5067 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20080114966.pdf [firstpage_image] =>[orig_patent_app_number] => 11586007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586007
Determining register availability for register renaming Oct 24, 2006 Issued
Array ( [id] => 7687978 [patent_doc_number] => 20070106720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Reconfigurable signal processor architecture using multiple complex multiply-accumulate units' [patent_app_type] => utility [patent_app_number] => 11/584175 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4903 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106720.pdf [firstpage_image] =>[orig_patent_app_number] => 11584175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584175
Reconfigurable signal processor architecture using multiple complex multiply-accumulate units Oct 19, 2006 Abandoned
Array ( [id] => 5042203 [patent_doc_number] => 20070094485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Data processing system and method' [patent_app_type] => utility [patent_app_number] => 11/542118 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3579 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094485.pdf [firstpage_image] =>[orig_patent_app_number] => 11542118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542118
Loop data processing system and method for dividing a loop into phases Oct 3, 2006 Issued
Array ( [id] => 4590965 [patent_doc_number] => 07827393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Branch prediction apparatus, its method and processor' [patent_app_type] => utility [patent_app_number] => 11/515971 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5785 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827393.pdf [firstpage_image] =>[orig_patent_app_number] => 11515971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515971
Branch prediction apparatus, its method and processor Sep 5, 2006 Issued
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