Search

Aimee J. Li

Examiner (ID: 2492)

Most Active Art Unit
2183
Art Unit(s)
2195, 2137, 2183, 2100
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 823389 [patent_doc_number] => 07409534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-05 [patent_title] => 'Automatic and transparent hardware conversion of traditional control flow to predicates' [patent_app_type] => utility [patent_app_number] => 11/515374 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3518 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409534.pdf [firstpage_image] =>[orig_patent_app_number] => 11515374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515374
Automatic and transparent hardware conversion of traditional control flow to predicates Aug 30, 2006 Issued
Array ( [id] => 856291 [patent_doc_number] => 07380108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Automatic and transparent hardware conversion of traditional control flow to predicates' [patent_app_type] => utility [patent_app_number] => 11/515220 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3516 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380108.pdf [firstpage_image] =>[orig_patent_app_number] => 11515220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515220
Automatic and transparent hardware conversion of traditional control flow to predicates Aug 30, 2006 Issued
Array ( [id] => 137223 [patent_doc_number] => 07698542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Circuit and method for comparing program counter values' [patent_app_type] => utility [patent_app_number] => 11/467370 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3576 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698542.pdf [firstpage_image] =>[orig_patent_app_number] => 11467370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467370
Circuit and method for comparing program counter values Aug 24, 2006 Issued
Array ( [id] => 7972123 [patent_doc_number] => 07941640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Secure processors having encoded instructions' [patent_app_type] => utility [patent_app_number] => 11/510006 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4245 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941640.pdf [firstpage_image] =>[orig_patent_app_number] => 11510006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510006
Secure processors having encoded instructions Aug 24, 2006 Issued
Array ( [id] => 5006564 [patent_doc_number] => 20070204137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture' [patent_app_type] => utility [patent_app_number] => 11/466621 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 51563 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204137.pdf [firstpage_image] =>[orig_patent_app_number] => 11466621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466621
Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture Aug 22, 2006 Issued
Array ( [id] => 5190723 [patent_doc_number] => 20070169032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Data processing system and method' [patent_app_type] => utility [patent_app_number] => 11/506887 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3526 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20070169032.pdf [firstpage_image] =>[orig_patent_app_number] => 11506887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506887
Register allocation method and system for program compiling Aug 20, 2006 Issued
Array ( [id] => 4671622 [patent_doc_number] => 20080046683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'System and method of processing data using scalar/vector instructions' [patent_app_type] => utility [patent_app_number] => 11/506584 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7655 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046683.pdf [firstpage_image] =>[orig_patent_app_number] => 11506584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506584
System and method of processing data using scalar/vector instructions Aug 17, 2006 Issued
Array ( [id] => 4671623 [patent_doc_number] => 20080046684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'MULTITHREADED MULTICORE UNIPROCESSOR AND A HETEROGENEOUS MULTIPROCESSOR INCORPORATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/465247 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4601 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046684.pdf [firstpage_image] =>[orig_patent_app_number] => 11465247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465247
MULTITHREADED MULTICORE UNIPROCESSOR AND A HETEROGENEOUS MULTIPROCESSOR INCORPORATING THE SAME Aug 16, 2006 Abandoned
Array ( [id] => 313138 [patent_doc_number] => 07529916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Data processing apparatus and method for controlling access to registers' [patent_app_type] => utility [patent_app_number] => 11/504780 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9701 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529916.pdf [firstpage_image] =>[orig_patent_app_number] => 11504780 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504780
Data processing apparatus and method for controlling access to registers Aug 15, 2006 Issued
Array ( [id] => 4671621 [patent_doc_number] => 20080046682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'DATA PROCESSING UNIT AND METHOD FOR PARALLEL VECTOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 11/464683 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3755 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046682.pdf [firstpage_image] =>[orig_patent_app_number] => 11464683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464683
Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length Aug 14, 2006 Issued
Array ( [id] => 5627070 [patent_doc_number] => 20060265575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'VIRTUAL REGISTER SET EXPANDING PROCESSOR INTERNAL STORAGE' [patent_app_type] => utility [patent_app_number] => 11/461361 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5078 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265575.pdf [firstpage_image] =>[orig_patent_app_number] => 11461361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461361
VIRTUAL REGISTER SET EXPANDING PROCESSOR INTERNAL STORAGE Jul 30, 2006 Abandoned
Array ( [id] => 5305687 [patent_doc_number] => 20090300339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'LSI FOR IC CARD' [patent_app_type] => utility [patent_app_number] => 12/063008 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1690 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300339.pdf [firstpage_image] =>[orig_patent_app_number] => 12063008 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/063008
LSI FOR IC CARD Jul 10, 2006 Abandoned
Array ( [id] => 343152 [patent_doc_number] => 07502913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Switch prefetch in a multicore computer chip' [patent_app_type] => utility [patent_app_number] => 11/454245 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4147 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502913.pdf [firstpage_image] =>[orig_patent_app_number] => 11454245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454245
Switch prefetch in a multicore computer chip Jun 15, 2006 Issued
Array ( [id] => 316904 [patent_doc_number] => 07526637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Adaptive execution method for multithreaded processor-based parallel system' [patent_app_type] => utility [patent_app_number] => 11/453288 [patent_app_country] => US [patent_app_date] => 2006-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7191 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526637.pdf [firstpage_image] =>[orig_patent_app_number] => 11453288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453288
Adaptive execution method for multithreaded processor-based parallel system Jun 14, 2006 Issued
Array ( [id] => 329502 [patent_doc_number] => 07516310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 11/422996 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3496 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516310.pdf [firstpage_image] =>[orig_patent_app_number] => 11422996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422996
Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor Jun 7, 2006 Issued
Array ( [id] => 5167147 [patent_doc_number] => 20070288736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Local and Global Branch Prediction Information Storage' [patent_app_type] => utility [patent_app_number] => 11/422927 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21520 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288736.pdf [firstpage_image] =>[orig_patent_app_number] => 11422927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422927
Local and global branch prediction information storage Jun 7, 2006 Issued
Array ( [id] => 5167137 [patent_doc_number] => 20070288726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Simple Load and Store Disambiguation and Scheduling at Predecode' [patent_app_type] => utility [patent_app_number] => 11/422647 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17625 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288726.pdf [firstpage_image] =>[orig_patent_app_number] => 11422647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422647
Simple load and store disambiguation and scheduling at predecode Jun 6, 2006 Issued
Array ( [id] => 5891621 [patent_doc_number] => 20060277235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'PERFORMING VARIABLE AND/OR BITWISE SHIFT OPERATION FOR A SHIFT INSTRUCTION THAT DOES NOT PROVIDE A VARIABLE OR BITWISE SHIFT OPTION' [patent_app_type] => utility [patent_app_number] => 11/422325 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5549 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277235.pdf [firstpage_image] =>[orig_patent_app_number] => 11422325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422325
Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option Jun 4, 2006 Issued
Array ( [id] => 355517 [patent_doc_number] => 07493468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing' [patent_app_type] => utility [patent_app_number] => 11/421512 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7391 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493468.pdf [firstpage_image] =>[orig_patent_app_number] => 11421512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421512
Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing May 31, 2006 Issued
Array ( [id] => 9652149 [patent_doc_number] => 08806183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Blank bit and processor instructions employing the blank bit' [patent_app_type] => utility [patent_app_number] => 11/345803 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11345803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/345803
Blank bit and processor instructions employing the blank bit Jan 31, 2006 Issued
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