Aimee J. Li

Array ( [id] => 9652149 [patent_doc_number] => 08806183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Blank bit and processor instructions employing the blank bit' [patent_app_type] => utility [patent_app_number] => 11/345803 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11345803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166631 [patent_doc_number] => 07673117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Operation apparatus' [patent_app_type] => utility [patent_app_number] => 11/343169 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 85 [patent_no_of_words] => 9818 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673117.pdf [firstpage_image] =>[orig_patent_app_number] => 11343169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 368264 [patent_doc_number] => 07480787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-20 [patent_title] => 'Method and structure for pipelining of SIMD conditional moves' [patent_app_type] => utility [patent_app_number] => 11/341001 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6273 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480787.pdf [firstpage_image] =>[orig_patent_app_number] => 11341001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5633474 [patent_doc_number] => 20060149945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Facilitating value prediction to support speculative program execution' [patent_app_type] => utility [patent_app_number] => 11/340076 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5760 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149945.pdf [firstpage_image] =>[orig_patent_app_number] => 11340076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5024738 [patent_doc_number] => 20070150705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Efficient counting for iterative instructions' [patent_app_type] => utility [patent_app_number] => 11/320262 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4825 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150705.pdf [firstpage_image] =>[orig_patent_app_number] => 11320262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4591961 [patent_doc_number] => 07836276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'System and method for processing thread groups in a SIMD architecture' [patent_app_type] => utility [patent_app_number] => 11/292614 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3461 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836276.pdf [firstpage_image] =>[orig_patent_app_number] => 11292614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17456 [patent_doc_number] => 07805596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Highly integrated multiprocessor system' [patent_app_type] => utility [patent_app_number] => 10/587553 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5646 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805596.pdf [firstpage_image] =>[orig_patent_app_number] => 10587553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5042381 [patent_doc_number] => 20070094663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Flexible ordered execution mechanism for multi-threaded processors' [patent_app_type] => utility [patent_app_number] => 11/258307 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094663.pdf [firstpage_image] =>[orig_patent_app_number] => 11258307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5195251 [patent_doc_number] => 20070083736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Instruction packer for digital signal processor' [patent_app_type] => utility [patent_app_number] => 11/244564 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083736.pdf [firstpage_image] =>[orig_patent_app_number] => 11244564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867122 [patent_doc_number] => 20060101253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Computing machine with redundancy and related systems and methods' [patent_app_type] => utility [patent_app_number] => 11/243507 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20743 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101253.pdf [firstpage_image] =>[orig_patent_app_number] => 11243507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5689879 [patent_doc_number] => 20060288194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Real-time processor' [patent_app_type] => utility [patent_app_number] => 11/240535 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10402 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20060288194.pdf [firstpage_image] =>[orig_patent_app_number] => 11240535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 305624 [patent_doc_number] => 07536533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'MCU based motor controller with pre-load register and DMA controller' [patent_app_type] => utility [patent_app_number] => 11/240250 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536533.pdf [firstpage_image] =>[orig_patent_app_number] => 11240250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173569 [patent_doc_number] => 20070074008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Mixed mode floating-point pipeline with extended functions' [patent_app_type] => utility [patent_app_number] => 11/237006 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074008.pdf [firstpage_image] =>[orig_patent_app_number] => 11237006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173570 [patent_doc_number] => 20070074009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Scalable parallel pipeline floating-point unit for vector processing' [patent_app_type] => utility [patent_app_number] => 11/237548 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074009.pdf [firstpage_image] =>[orig_patent_app_number] => 11237548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173566 [patent_doc_number] => 20070074005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method and apparatus for issuing instructions from an issue queue in an information handling system' [patent_app_type] => utility [patent_app_number] => 11/236838 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074005.pdf [firstpage_image] =>[orig_patent_app_number] => 11236838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 839894 [patent_doc_number] => 07395418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread' [patent_app_type] => utility [patent_app_number] => 11/234669 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2347 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395418.pdf [firstpage_image] =>[orig_patent_app_number] => 11234669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867100 [patent_doc_number] => 20060101231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Semiconductor signal processing device' [patent_app_type] => utility [patent_app_number] => 11/225151 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19018 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101231.pdf [firstpage_image] =>[orig_patent_app_number] => 11225151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 472878 [patent_doc_number] => 07234045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Apparatus and method for handling BTAC branches that wrap across instruction cache lines' [patent_app_type] => utility [patent_app_number] => 11/208302 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234045.pdf [firstpage_image] =>[orig_patent_app_number] => 11208302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5752632 [patent_doc_number] => 20060221781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Information processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/157428 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221781.pdf [firstpage_image] =>[orig_patent_app_number] => 11157428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7021566 [patent_doc_number] => 20050223192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Instruction sets for processors' [patent_app_type] => utility [patent_app_number] => 11/147689 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9053 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223192.pdf [firstpage_image] =>[orig_patent_app_number] => 11147689 [rel_patent_id] =>[rel_patent_doc_number] =>)