Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7057342 [patent_doc_number] => 20050278517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Systems and methods for performing branch prediction in a variable length instruction set microprocessor' [patent_app_type] => utility [patent_app_number] => 11/132428 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5485 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278517.pdf [firstpage_image] =>[orig_patent_app_number] => 11132428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132428
Systems and methods for performing branch prediction in a variable length instruction set microprocessor May 18, 2005 Abandoned
Array ( [id] => 4472234 [patent_doc_number] => 07937572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Run-time selection of feed-back connections in a multiple-instruction word processor' [patent_app_type] => utility [patent_app_number] => 11/568984 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6662 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937572.pdf [firstpage_image] =>[orig_patent_app_number] => 11568984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568984
Run-time selection of feed-back connections in a multiple-instruction word processor May 8, 2005 Issued
Array ( [id] => 128034 [patent_doc_number] => 07707395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Data processing system with trace co-processor' [patent_app_type] => utility [patent_app_number] => 11/596326 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3050 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707395.pdf [firstpage_image] =>[orig_patent_app_number] => 11596326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596326
Data processing system with trace co-processor May 3, 2005 Issued
Array ( [id] => 5852886 [patent_doc_number] => 20060236077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Microprocessor access of operand stack as a register file using native instructions' [patent_app_type] => utility [patent_app_number] => 11/107235 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6264 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236077.pdf [firstpage_image] =>[orig_patent_app_number] => 11107235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/107235
Microprocessor access of operand stack as a register file using native instructions Apr 14, 2005 Issued
Array ( [id] => 5755724 [patent_doc_number] => 20060224873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Acquiring instruction addresses associated with performance monitoring events' [patent_app_type] => utility [patent_app_number] => 11/095072 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10764 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20060224873.pdf [firstpage_image] =>[orig_patent_app_number] => 11095072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095072
Acquiring instruction addresses associated with performance monitoring events Mar 30, 2005 Issued
Array ( [id] => 7021568 [patent_doc_number] => 20050223194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method and structure for explicit software control using scoreboard status information' [patent_app_type] => utility [patent_app_number] => 11/082282 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4318 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223194.pdf [firstpage_image] =>[orig_patent_app_number] => 11082282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082282
Method and structure for explicit software control using scoreboard status information Mar 15, 2005 Issued
Array ( [id] => 206459 [patent_doc_number] => 07634640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Data processing apparatus having program counter sensor' [patent_app_type] => utility [patent_app_number] => 11/070843 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/634/07634640.pdf [firstpage_image] =>[orig_patent_app_number] => 11070843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070843
Data processing apparatus having program counter sensor Feb 23, 2005 Issued
Array ( [id] => 17443 [patent_doc_number] => 07805591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Method and system for dual-core processing' [patent_app_type] => utility [patent_app_number] => 11/062387 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2588 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805591.pdf [firstpage_image] =>[orig_patent_app_number] => 11062387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062387
Method and system for dual-core processing Feb 21, 2005 Issued
Array ( [id] => 107689 [patent_doc_number] => 07725678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method and apparatus for producing an index vector for use in performing a vector permute operation' [patent_app_type] => utility [patent_app_number] => 11/060208 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2468 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725678.pdf [firstpage_image] =>[orig_patent_app_number] => 11060208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060208
Method and apparatus for producing an index vector for use in performing a vector permute operation Feb 16, 2005 Issued
Array ( [id] => 900130 [patent_doc_number] => 07343476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Intelligent SMT thread hang detect taking into account shared resource contention/blocking' [patent_app_type] => utility [patent_app_number] => 11/055044 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7299 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 870 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343476.pdf [firstpage_image] =>[orig_patent_app_number] => 11055044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055044
Intelligent SMT thread hang detect taking into account shared resource contention/blocking Feb 9, 2005 Issued
Array ( [id] => 7100350 [patent_doc_number] => 20050132176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method for identifying basic blocks with conditional delay slot instructions' [patent_app_type] => utility [patent_app_number] => 11/046439 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11659 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132176.pdf [firstpage_image] =>[orig_patent_app_number] => 11046439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046439
Method for identifying basic blocks with conditional delay slot instructions Jan 27, 2005 Issued
Array ( [id] => 6932553 [patent_doc_number] => 20050283588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Instruction control apparatus, function unit, program conversion apparatus, and language processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/044631 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16754 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283588.pdf [firstpage_image] =>[orig_patent_app_number] => 11044631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044631
Instruction control apparatus, function unit, program conversion apparatus, and language processing apparatus Jan 27, 2005 Abandoned
Array ( [id] => 7185502 [patent_doc_number] => 20050125633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions' [patent_app_type] => utility [patent_app_number] => 11/035434 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10462 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125633.pdf [firstpage_image] =>[orig_patent_app_number] => 11035434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035434
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions Jan 11, 2005 Issued
Array ( [id] => 5633450 [patent_doc_number] => 20060149921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method and apparatus for sharing control components across multiple processing elements' [patent_app_type] => utility [patent_app_number] => 11/022109 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8876 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149921.pdf [firstpage_image] =>[orig_patent_app_number] => 11022109 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022109
Method and apparatus for sharing control components across multiple processing elements Dec 19, 2004 Abandoned
Array ( [id] => 823382 [patent_doc_number] => 07409530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method and apparatus for compressing VLIW instruction and sharing subinstructions' [patent_app_type] => utility [patent_app_number] => 11/015717 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6218 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409530.pdf [firstpage_image] =>[orig_patent_app_number] => 11015717 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015717
Method and apparatus for compressing VLIW instruction and sharing subinstructions Dec 16, 2004 Issued
Array ( [id] => 6999651 [patent_doc_number] => 20050138327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'VLIW digital signal processor for achieving improved binary translation' [patent_app_type] => utility [patent_app_number] => 11/008927 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3074 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138327.pdf [firstpage_image] =>[orig_patent_app_number] => 11008927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008927
VLIW digital signal processor for achieving improved binary translation Dec 12, 2004 Issued
Array ( [id] => 5633452 [patent_doc_number] => 20060149923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Microprocessor optimized for algorithmic processing' [patent_app_type] => utility [patent_app_number] => 11/007745 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6302 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149923.pdf [firstpage_image] =>[orig_patent_app_number] => 11007745 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/007745
Microprocessor optimized for algorithmic processing Dec 7, 2004 Abandoned
Array ( [id] => 421330 [patent_doc_number] => 07278014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'System and method for simulating hardware interrupts' [patent_app_type] => utility [patent_app_number] => 11/002533 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4448 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/278/07278014.pdf [firstpage_image] =>[orig_patent_app_number] => 11002533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002533
System and method for simulating hardware interrupts Dec 1, 2004 Issued
Array ( [id] => 6992443 [patent_doc_number] => 20050091480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Computer system and method for executing interrupt instructions in operating modes' [patent_app_type] => utility [patent_app_number] => 10/982217 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3119 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091480.pdf [firstpage_image] =>[orig_patent_app_number] => 10982217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982217
Computer system and method for executing interrupt instructions in operating modes Nov 4, 2004 Abandoned
Array ( [id] => 223457 [patent_doc_number] => 07610473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor' [patent_app_type] => utility [patent_app_number] => 10/928746 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9711 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610473.pdf [firstpage_image] =>[orig_patent_app_number] => 10928746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928746
Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor Aug 26, 2004 Issued
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