Aimee J. Li

Array ( [id] => 7091798 [patent_doc_number] => 20050010745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Dynamic field patchable microarchitecture' [patent_app_type] => utility [patent_app_number] => 10/914105 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010745.pdf [firstpage_image] =>[orig_patent_app_number] => 10914105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5795174 [patent_doc_number] => 20060015855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Systems and methods for replacing NOP instructions in a first program with instructions of a second program' [patent_app_type] => utility [patent_app_number] => 10/890088 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7970 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015855.pdf [firstpage_image] =>[orig_patent_app_number] => 10890088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5896451 [patent_doc_number] => 20060004990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Distributed processing in a multiple processing unit environment' [patent_app_type] => utility [patent_app_number] => 10/884602 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004990.pdf [firstpage_image] =>[orig_patent_app_number] => 10884602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730398 [patent_doc_number] => 20080209149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Processor Architecture for Exact Pointer Identification' [patent_app_type] => utility [patent_app_number] => 10/563122 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6092 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209149.pdf [firstpage_image] =>[orig_patent_app_number] => 10563122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7030459 [patent_doc_number] => 20050021926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method and apparatus for efficient loading and storing of vectors' [patent_app_type] => utility [patent_app_number] => 10/849804 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9465 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20050021926.pdf [firstpage_image] =>[orig_patent_app_number] => 10849804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 329504 [patent_doc_number] => 07516312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Presbyopic branch target prefetch method and apparatus' [patent_app_type] => utility [patent_app_number] => 10/817263 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5053 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516312.pdf [firstpage_image] =>[orig_patent_app_number] => 10817263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 806124 [patent_doc_number] => 07424596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Code interpretation using stack state information' [patent_app_type] => utility [patent_app_number] => 10/813599 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424596.pdf [firstpage_image] =>[orig_patent_app_number] => 10813599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7260010 [patent_doc_number] => 20050076189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Method and apparatus for pipeline processing a chain of processing instructions' [patent_app_type] => utility [patent_app_number] => 10/812132 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2369 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076189.pdf [firstpage_image] =>[orig_patent_app_number] => 10812132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962332 [patent_doc_number] => 20050216700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Reconfigurable parallelism architecture' [patent_app_type] => utility [patent_app_number] => 10/813790 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5021 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216700.pdf [firstpage_image] =>[orig_patent_app_number] => 10813790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962342 [patent_doc_number] => 20050216703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor' [patent_app_type] => utility [patent_app_number] => 10/810235 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3971 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216703.pdf [firstpage_image] =>[orig_patent_app_number] => 10810235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962368 [patent_doc_number] => 20050216714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Method and apparatus for predicting confidence and value' [patent_app_type] => utility [patent_app_number] => 10/809957 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4051 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216714.pdf [firstpage_image] =>[orig_patent_app_number] => 10809957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447454 [patent_doc_number] => 07930526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Compare and branch mechanism' [patent_app_type] => utility [patent_app_number] => 10/807499 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4411 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930526.pdf [firstpage_image] =>[orig_patent_app_number] => 10807499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6962364 [patent_doc_number] => 20050216711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Null exception handling' [patent_app_type] => utility [patent_app_number] => 10/807498 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2880 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216711.pdf [firstpage_image] =>[orig_patent_app_number] => 10807498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 106835 [patent_doc_number] => 07730284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Pipelined instruction processor with data bypassing and disabling circuit' [patent_app_type] => utility [patent_app_number] => 10/549368 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5111 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730284.pdf [firstpage_image] =>[orig_patent_app_number] => 10549368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6953871 [patent_doc_number] => 20050228966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Processor system and data processing method' [patent_app_type] => utility [patent_app_number] => 10/800631 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4007 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20050228966.pdf [firstpage_image] =>[orig_patent_app_number] => 10800631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7258982 [patent_doc_number] => 20040240648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Dynamic processing of data processing instructions' [patent_app_type] => new [patent_app_number] => 10/792274 [patent_app_country] => US [patent_app_date] => 2004-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3043 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240648.pdf [firstpage_image] =>[orig_patent_app_number] => 10792274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7676202 [patent_doc_number] => 20040153625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Array-type processor' [patent_app_type] => new [patent_app_number] => 10/761365 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5355 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153625.pdf [firstpage_image] =>[orig_patent_app_number] => 10761365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7123749 [patent_doc_number] => 20050015578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Two-bit branch prediction scheme using reduced memory size' [patent_app_type] => utility [patent_app_number] => 10/744517 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3259 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20050015578.pdf [firstpage_image] =>[orig_patent_app_number] => 10744517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7100339 [patent_doc_number] => 20050132173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and apparatus for allocating entries in a branch target buffer' [patent_app_type] => utility [patent_app_number] => 10/736393 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13765 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132173.pdf [firstpage_image] =>[orig_patent_app_number] => 10736393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7148909 [patent_doc_number] => 20050120192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Scalable rename map table recovery' [patent_app_type] => utility [patent_app_number] => 10/724876 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6191 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20050120192.pdf [firstpage_image] =>[orig_patent_app_number] => 10724876 [rel_patent_id] =>[rel_patent_doc_number] =>)