Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6907063 [patent_doc_number] => 20050102458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation' [patent_app_type] => utility [patent_app_number] => 10/712473 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6096 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102458.pdf [firstpage_image] =>[orig_patent_app_number] => 10712473 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712473
Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation Nov 11, 2003 Issued
Array ( [id] => 362554 [patent_doc_number] => 07487333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => utility [patent_app_number] => 10/700485 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 31947 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487333.pdf [firstpage_image] =>[orig_patent_app_number] => 10700485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700485
High-performance, superscalar-based computer system with out-of-order instruction execution Nov 4, 2003 Issued
Array ( [id] => 127998 [patent_doc_number] => 07707389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Multi-ISA instruction fetch unit for a processor, and applications thereof' [patent_app_type] => utility [patent_app_number] => 10/698061 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6523 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707389.pdf [firstpage_image] =>[orig_patent_app_number] => 10698061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/698061
Multi-ISA instruction fetch unit for a processor, and applications thereof Oct 30, 2003 Issued
Array ( [id] => 37521 [patent_doc_number] => 07793072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands' [patent_app_type] => utility [patent_app_number] => 10/699571 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793072.pdf [firstpage_image] =>[orig_patent_app_number] => 10699571 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699571
Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands Oct 30, 2003 Issued
Array ( [id] => 343154 [patent_doc_number] => 07502915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'System and method using embedded microprocessor as a node in an adaptable computing machine' [patent_app_type] => utility [patent_app_number] => 10/673678 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8164 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502915.pdf [firstpage_image] =>[orig_patent_app_number] => 10673678 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/673678
System and method using embedded microprocessor as a node in an adaptable computing machine Sep 28, 2003 Issued
Array ( [id] => 7271386 [patent_doc_number] => 20040059904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Program-controlled unit' [patent_app_type] => new [patent_app_number] => 10/667720 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2040 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059904.pdf [firstpage_image] =>[orig_patent_app_number] => 10667720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/667720
Program-controlled unit Sep 21, 2003 Abandoned
Array ( [id] => 7013533 [patent_doc_number] => 20050066151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method and apparatus for handling predicated instructions in an out-of-order processor' [patent_app_type] => utility [patent_app_number] => 10/666343 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3382 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066151.pdf [firstpage_image] =>[orig_patent_app_number] => 10666343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666343
Method and apparatus for handling predicated instructions in an out-of-order processor Sep 18, 2003 Abandoned
Array ( [id] => 873499 [patent_doc_number] => 07366877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Speculative instruction issue in a simultaneously multithreaded processor' [patent_app_type] => utility [patent_app_number] => 10/664384 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3634 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366877.pdf [firstpage_image] =>[orig_patent_app_number] => 10664384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/664384
Speculative instruction issue in a simultaneously multithreaded processor Sep 16, 2003 Issued
Array ( [id] => 7129293 [patent_doc_number] => 20050060577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Interrupt verification support mechanism' [patent_app_type] => utility [patent_app_number] => 10/664055 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8032 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20050060577.pdf [firstpage_image] =>[orig_patent_app_number] => 10664055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/664055
Interrupt verification support mechanism Sep 16, 2003 Issued
Array ( [id] => 7293443 [patent_doc_number] => 20040111589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Asynchronous multiple-order issue system architecture' [patent_app_type] => new [patent_app_number] => 10/667152 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5328 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111589.pdf [firstpage_image] =>[orig_patent_app_number] => 10667152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/667152
Asynchronous multiple-order issue system architecture Sep 15, 2003 Issued
Array ( [id] => 7160360 [patent_doc_number] => 20050027974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Method and system for conserving resources in an instruction pipeline' [patent_app_type] => utility [patent_app_number] => 10/630686 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2468 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027974.pdf [firstpage_image] =>[orig_patent_app_number] => 10630686 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630686
Method and system for conserving resources in an instruction pipeline Jul 30, 2003 Abandoned
Array ( [id] => 7293444 [patent_doc_number] => 20040111590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Self-configuring processing element' [patent_app_type] => new [patent_app_number] => 10/625186 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7657 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111590.pdf [firstpage_image] =>[orig_patent_app_number] => 10625186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625186
Self-configuring processing element Jul 22, 2003 Abandoned
Array ( [id] => 7474381 [patent_doc_number] => 20040103267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Data processor having cache memory' [patent_app_type] => new [patent_app_number] => 10/624838 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20040103267.pdf [firstpage_image] =>[orig_patent_app_number] => 10624838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624838
Data processor having cache memory Jul 22, 2003 Abandoned
Array ( [id] => 7473770 [patent_doc_number] => 20040054818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Flexible results pipeline for processing element' [patent_app_type] => new [patent_app_number] => 10/442667 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2746 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054818.pdf [firstpage_image] =>[orig_patent_app_number] => 10442667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442667
Processing element and method connecting registers to processing logic in a plurality of configurations May 19, 2003 Issued
Array ( [id] => 929622 [patent_doc_number] => 07315934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Data processor and program for processing a data matrix' [patent_app_type] => utility [patent_app_number] => 10/377328 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 120 [patent_no_of_words] => 25708 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315934.pdf [firstpage_image] =>[orig_patent_app_number] => 10377328 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377328
Data processor and program for processing a data matrix Feb 27, 2003 Issued
Array ( [id] => 7474194 [patent_doc_number] => 20040168041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Flexible interface device' [patent_app_type] => new [patent_app_number] => 10/374147 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4363 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168041.pdf [firstpage_image] =>[orig_patent_app_number] => 10374147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/374147
Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices Feb 24, 2003 Issued
Array ( [id] => 7445353 [patent_doc_number] => 20040003203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Instruction fetch control device and instruction fetch control method' [patent_app_type] => new [patent_app_number] => 10/368670 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10554 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003203.pdf [firstpage_image] =>[orig_patent_app_number] => 10368670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/368670
Instruction fetch control device and method thereof with dynamic configuration of instruction buffers Feb 19, 2003 Issued
Array ( [id] => 7372611 [patent_doc_number] => 20040006685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Processor and instruction control method' [patent_app_type] => new [patent_app_number] => 10/347337 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11550 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20040006685.pdf [firstpage_image] =>[orig_patent_app_number] => 10347337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347337
Processor and instruction control method Jan 20, 2003 Issued
Array ( [id] => 7312625 [patent_doc_number] => 20040143728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Data processing apparatus and method for swapping data values' [patent_app_type] => new [patent_app_number] => 10/347481 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7184 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143728.pdf [firstpage_image] =>[orig_patent_app_number] => 10347481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347481
Data processing apparatus and method for utilizing endianess independent data values Jan 20, 2003 Issued
Array ( [id] => 7328711 [patent_doc_number] => 20040139297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'System and method for scalable interconnection of adaptive processor nodes for clustered computer systems' [patent_app_type] => new [patent_app_number] => 10/340400 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3478 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139297.pdf [firstpage_image] =>[orig_patent_app_number] => 10340400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340400
System and method for scalable interconnection of adaptive processor nodes for clustered computer systems Jan 9, 2003 Abandoned
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