
Aimee J. Li
Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2195, 2137, 2100 |
| Total Applications | 539 |
| Issued Applications | 378 |
| Pending Applications | 20 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6907063
[patent_doc_number] => 20050102458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation'
[patent_app_type] => utility
[patent_app_number] => 10/712473
[patent_app_country] => US
[patent_app_date] => 2003-11-12
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20050102458.pdf
[firstpage_image] =>[orig_patent_app_number] => 10712473
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/712473 | Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation | Nov 11, 2003 | Issued |
Array
(
[id] => 362554
[patent_doc_number] => 07487333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution'
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[patent_app_number] => 10/700485
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/700485 | High-performance, superscalar-based computer system with out-of-order instruction execution | Nov 4, 2003 | Issued |
Array
(
[id] => 127998
[patent_doc_number] => 07707389
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[patent_issue_date] => 2010-04-27
[patent_title] => 'Multi-ISA instruction fetch unit for a processor, and applications thereof'
[patent_app_type] => utility
[patent_app_number] => 10/698061
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/698061 | Multi-ISA instruction fetch unit for a processor, and applications thereof | Oct 30, 2003 | Issued |
Array
(
[id] => 37521
[patent_doc_number] => 07793072
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands'
[patent_app_type] => utility
[patent_app_number] => 10/699571
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Array
(
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[patent_issue_date] => 2009-03-10
[patent_title] => 'System and method using embedded microprocessor as a node in an adaptable computing machine'
[patent_app_type] => utility
[patent_app_number] => 10/673678
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/673678 | System and method using embedded microprocessor as a node in an adaptable computing machine | Sep 28, 2003 | Issued |
Array
(
[id] => 7271386
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[patent_title] => 'Program-controlled unit'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/667720 | Program-controlled unit | Sep 21, 2003 | Abandoned |
Array
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[patent_title] => 'Method and apparatus for handling predicated instructions in an out-of-order processor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/666343 | Method and apparatus for handling predicated instructions in an out-of-order processor | Sep 18, 2003 | Abandoned |
Array
(
[id] => 873499
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[patent_issue_date] => 2008-04-29
[patent_title] => 'Speculative instruction issue in a simultaneously multithreaded processor'
[patent_app_type] => utility
[patent_app_number] => 10/664384
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Array
(
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Array
(
[id] => 7293443
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[patent_title] => 'Asynchronous multiple-order issue system architecture'
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Array
(
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[patent_title] => 'Method and system for conserving resources in an instruction pipeline'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/625186 | Self-configuring processing element | Jul 22, 2003 | Abandoned |
Array
(
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/347481 | Data processing apparatus and method for utilizing endianess independent data values | Jan 20, 2003 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340400 | System and method for scalable interconnection of adaptive processor nodes for clustered computer systems | Jan 9, 2003 | Abandoned |