Aimee J. Li

Array ( [id] => 6763047 [patent_doc_number] => 20030126409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Store sets poison propagation' [patent_app_type] => new [patent_app_number] => 10/034219 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5235 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126409.pdf [firstpage_image] =>[orig_patent_app_number] => 10034219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532565 [patent_doc_number] => 07844799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Method and system for pipeline reduction' [patent_app_type] => utility [patent_app_number] => 09/683383 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4631 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844799.pdf [firstpage_image] =>[orig_patent_app_number] => 09683383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 79393 [patent_doc_number] => 07752419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-06 [patent_title] => 'Method and system for managing hardware resources to implement system functions using an adaptive computing architecture' [patent_app_type] => utility [patent_app_number] => 10/015530 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9652 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/752/07752419.pdf [firstpage_image] =>[orig_patent_app_number] => 10015530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6310617 [patent_doc_number] => 20020095562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Arithmetic unit comprising a memory shared by a plurality of processors' [patent_app_type] => new [patent_app_number] => 09/972157 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20020095562.pdf [firstpage_image] =>[orig_patent_app_number] => 09972157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 684752 [patent_doc_number] => 07085919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Predicate prediction based on a predicated predicate value' [patent_app_type] => utility [patent_app_number] => 09/973429 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085919.pdf [firstpage_image] =>[orig_patent_app_number] => 09973429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6388987 [patent_doc_number] => 20020120830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => ' Data processor assigning the same operation code to multiple operations' [patent_app_type] => new [patent_app_number] => 09/971607 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11605 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120830.pdf [firstpage_image] =>[orig_patent_app_number] => 09971607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 953342 [patent_doc_number] => 06961844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline' [patent_app_type] => utility [patent_app_number] => 09/972404 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8523 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961844.pdf [firstpage_image] =>[orig_patent_app_number] => 09972404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 782269 [patent_doc_number] => 06996701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Computer system employing pipeline operation' [patent_app_type] => utility [patent_app_number] => 09/963894 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10279 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996701.pdf [firstpage_image] =>[orig_patent_app_number] => 09963894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1030623 [patent_doc_number] => 06883090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method for cancelling conditional delay slot instructions' [patent_app_type] => utility [patent_app_number] => 09/961625 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11664 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883090.pdf [firstpage_image] =>[orig_patent_app_number] => 09961625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1055835 [patent_doc_number] => 06859874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method for identifying basic blocks with conditional delay slot instructions' [patent_app_type] => utility [patent_app_number] => 09/961579 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11624 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859874.pdf [firstpage_image] =>[orig_patent_app_number] => 09961579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6211570 [patent_doc_number] => 20020073302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method and apparatus for caching short program loops within an instruction FIFO' [patent_app_type] => new [patent_app_number] => 09/953723 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2803 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073302.pdf [firstpage_image] =>[orig_patent_app_number] => 09953723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6532134 [patent_doc_number] => 20020026569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Method and apparatus for efficient loading and storing of vectors' [patent_app_type] => new [patent_app_number] => 09/918524 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9534 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026569.pdf [firstpage_image] =>[orig_patent_app_number] => 09918524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6746655 [patent_doc_number] => 20030023838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Novel fetch branch architecture for reducing branch penalty without branch prediction' [patent_app_type] => new [patent_app_number] => 09/917290 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023838.pdf [firstpage_image] =>[orig_patent_app_number] => 09917290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5926536 [patent_doc_number] => 20020116596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Digital signal processor with parallel architecture' [patent_app_type] => new [patent_app_number] => 09/915761 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6092 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116596.pdf [firstpage_image] =>[orig_patent_app_number] => 09915761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 469380 [patent_doc_number] => 07240186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method to avoid resource contention in the presence of exceptions' [patent_app_type] => utility [patent_app_number] => 09/906345 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240186.pdf [firstpage_image] =>[orig_patent_app_number] => 09906345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6946662 [patent_doc_number] => 20050198479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Apparatus and method for handling BTAC branches that wrap across instruction cache lines' [patent_app_type] => utility [patent_app_number] => 09/906381 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10807 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198479.pdf [firstpage_image] =>[orig_patent_app_number] => 09906381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 637525 [patent_doc_number] => 07130989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Processor adapted to receive different instruction sets' [patent_app_type] => utility [patent_app_number] => 09/903208 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9052 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130989.pdf [firstpage_image] =>[orig_patent_app_number] => 09903208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6757484 [patent_doc_number] => 20030005261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method and apparatus for attaching accelerator hardware containing internal state to a processing core' [patent_app_type] => new [patent_app_number] => 09/896423 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005261.pdf [firstpage_image] =>[orig_patent_app_number] => 09896423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 789419 [patent_doc_number] => 06988186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry' [patent_app_type] => utility [patent_app_number] => 09/894260 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10660 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988186.pdf [firstpage_image] =>[orig_patent_app_number] => 09894260 [rel_patent_id] =>[rel_patent_doc_number] =>)