Search

Aimee J. Li

Supervisory Patent Examiner (ID: 15085, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2137, 2100, 2183, 2195
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6632291 [patent_doc_number] => 20020066004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Storing stack operands in registers' [patent_app_type] => new [patent_app_number] => 09/887560 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066004.pdf [firstpage_image] =>[orig_patent_app_number] => 09887560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887560
Storing stack operands in registers Jun 24, 2001 Issued
Array ( [id] => 6632275 [patent_doc_number] => 20020066003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Restarting translated instructions' [patent_app_type] => new [patent_app_number] => 09/887559 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066003.pdf [firstpage_image] =>[orig_patent_app_number] => 09887559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887559
Restarting translated instructions Jun 24, 2001 Issued
Array ( [id] => 6757477 [patent_doc_number] => 20030005254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Compatible effective addressing with a dynamically reconfigurable data space word width' [patent_app_type] => new [patent_app_number] => 09/870462 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5367 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005254.pdf [firstpage_image] =>[orig_patent_app_number] => 09870462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870462
Compatible effective addressing with a dynamically reconfigurable data space word width May 31, 2001 Abandoned
Array ( [id] => 6675861 [patent_doc_number] => 20030061464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Digital signal controller instruction set and architecture' [patent_app_type] => new [patent_app_number] => 09/870457 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6670 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061464.pdf [firstpage_image] =>[orig_patent_app_number] => 09870457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870457
Digital signal controller instruction set and architecture May 31, 2001 Abandoned
Array ( [id] => 6265440 [patent_doc_number] => 20020188830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Bit replacement and extraction instructions' [patent_app_type] => new [patent_app_number] => 09/870637 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4497 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188830.pdf [firstpage_image] =>[orig_patent_app_number] => 09870637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870637
Bit replacement and extraction instructions May 31, 2001 Abandoned
Array ( [id] => 645561 [patent_doc_number] => 07124279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions' [patent_app_type] => utility [patent_app_number] => 09/862654 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10450 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124279.pdf [firstpage_image] =>[orig_patent_app_number] => 09862654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862654
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions May 21, 2001 Issued
Array ( [id] => 5836479 [patent_doc_number] => 20060248311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Method and apparatus of dsp resource allocation and use' [patent_app_type] => utility [patent_app_number] => 10/276414 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13282 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248311.pdf [firstpage_image] =>[orig_patent_app_number] => 10276414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/276414
Method and apparatus of dsp resource allocation and use May 13, 2001 Abandoned
09/853225 Secure system mode duration management May 10, 2001 Abandoned
Array ( [id] => 1033758 [patent_doc_number] => 06880072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Pipelined processor and method using a profile register storing the return from exception address of an executed instruction supplied by an exception program counter chain for code profiling' [patent_app_type] => utility [patent_app_number] => 09/850865 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4170 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/880/06880072.pdf [firstpage_image] =>[orig_patent_app_number] => 09850865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850865
Pipelined processor and method using a profile register storing the return from exception address of an executed instruction supplied by an exception program counter chain for code profiling May 7, 2001 Issued
Array ( [id] => 685453 [patent_doc_number] => 07082515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Data driven type information processing apparatus having deadlock breaking function' [patent_app_type] => utility [patent_app_number] => 09/842763 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6662 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082515.pdf [firstpage_image] =>[orig_patent_app_number] => 09842763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/842763
Data driven type information processing apparatus having deadlock breaking function Apr 26, 2001 Issued
Array ( [id] => 925054 [patent_doc_number] => 07320065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Multithread embedded processor with input/output capability' [patent_app_type] => utility [patent_app_number] => 09/843178 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320065.pdf [firstpage_image] =>[orig_patent_app_number] => 09843178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843178
Multithread embedded processor with input/output capability Apr 25, 2001 Issued
Array ( [id] => 508258 [patent_doc_number] => 07210025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-24 [patent_title] => 'Automatic and transparent hardware conversion of traditional control flow to predicates' [patent_app_type] => utility [patent_app_number] => 09/838678 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3494 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210025.pdf [firstpage_image] =>[orig_patent_app_number] => 09838678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838678
Automatic and transparent hardware conversion of traditional control flow to predicates Apr 18, 2001 Issued
Array ( [id] => 6988718 [patent_doc_number] => 20010037447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Simultaneous and redundantly threaded processor branch outcome queue' [patent_app_type] => new [patent_app_number] => 09/838078 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6079 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037447.pdf [firstpage_image] =>[orig_patent_app_number] => 09838078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838078
Simultaneous and redundantly threaded processor branch outcome queue Apr 18, 2001 Abandoned
Array ( [id] => 6181404 [patent_doc_number] => 20020156999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Mixed-mode hardware multithreading' [patent_app_type] => new [patent_app_number] => 09/838461 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3079 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156999.pdf [firstpage_image] =>[orig_patent_app_number] => 09838461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838461
Mixed-mode hardware multithreading Apr 18, 2001 Abandoned
Array ( [id] => 6115415 [patent_doc_number] => 20020174324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Fixed point unit pipeline allowing partial instruction execution during the instruction dispatch cycle' [patent_app_type] => new [patent_app_number] => 09/832544 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174324.pdf [firstpage_image] =>[orig_patent_app_number] => 09832544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832544
Fixed point unit pipeline allowing partial instruction execution during the instruction dispatch cycle Apr 10, 2001 Issued
Array ( [id] => 5910555 [patent_doc_number] => 20020144091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Method and apparatus for dynamic register management in a processor' [patent_app_type] => new [patent_app_number] => 09/825753 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 91 [patent_figures_cnt] => 91 [patent_no_of_words] => 14991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144091.pdf [firstpage_image] =>[orig_patent_app_number] => 09825753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825753
Method and apparatus for dynamic register management in a processor Apr 2, 2001 Abandoned
Array ( [id] => 933387 [patent_doc_number] => 06981132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Uniform register addressing using prefix byte' [patent_app_type] => utility [patent_app_number] => 09/825183 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981132.pdf [firstpage_image] =>[orig_patent_app_number] => 09825183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825183
Uniform register addressing using prefix byte Apr 1, 2001 Issued
Array ( [id] => 716769 [patent_doc_number] => 07058791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'Establishing a mode indication responsive to two or more indications' [patent_app_type] => utility [patent_app_number] => 09/824988 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15595 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058791.pdf [firstpage_image] =>[orig_patent_app_number] => 09824988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824988
Establishing a mode indication responsive to two or more indications Apr 1, 2001 Issued
Array ( [id] => 645578 [patent_doc_number] => 07124286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Establishing an operating mode in a processor' [patent_app_type] => utility [patent_app_number] => 09/824890 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 16307 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124286.pdf [firstpage_image] =>[orig_patent_app_number] => 09824890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824890
Establishing an operating mode in a processor Apr 1, 2001 Issued
Array ( [id] => 5910558 [patent_doc_number] => 20020144094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Retiring early-completion instructions to improve computer operation throughput' [patent_app_type] => new [patent_app_number] => 09/823403 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144094.pdf [firstpage_image] =>[orig_patent_app_number] => 09823403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823403
Retiring early-completion instructions to improve computer operation throughput Mar 29, 2001 Issued
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