Aimee J. Li

Array ( [id] => 645575 [patent_doc_number] => 07124285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Peak power reduction when updating future file' [patent_app_type] => utility [patent_app_number] => 09/823276 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2239 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124285.pdf [firstpage_image] =>[orig_patent_app_number] => 09823276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6099113 [patent_doc_number] => 20020053017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Register instructions for a multithreaded processor' [patent_app_type] => new [patent_app_number] => 09/811995 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053017.pdf [firstpage_image] =>[orig_patent_app_number] => 09811995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7001743 [patent_doc_number] => 20010054126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'SIMD type processor, method and apparatus for parallel processing, devices that use the SIMD type processor or the parallel processing apparatus, method and apparatus for image processing, computer product' [patent_app_type] => new [patent_app_number] => 09/801843 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 23777 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054126.pdf [firstpage_image] =>[orig_patent_app_number] => 09801843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 753089 [patent_doc_number] => 07028170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Processing architecture having a compare capability' [patent_app_type] => utility [patent_app_number] => 09/802291 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028170.pdf [firstpage_image] =>[orig_patent_app_number] => 09802291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6886996 [patent_doc_number] => 20010020265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Data processor with multi-command instruction words' [patent_app_type] => new [patent_app_number] => 09/794943 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3893 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020265.pdf [firstpage_image] =>[orig_patent_app_number] => 09794943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 761889 [patent_doc_number] => 07020767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Techniques for reducing the rate of instruction issuance' [patent_app_type] => utility [patent_app_number] => 09/792426 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7910 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020767.pdf [firstpage_image] =>[orig_patent_app_number] => 09792426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020088 [patent_doc_number] => 20020103990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Programmed load precession machine' [patent_app_type] => new [patent_app_number] => 09/776084 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6372 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103990.pdf [firstpage_image] =>[orig_patent_app_number] => 09776084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1037165 [patent_doc_number] => 06877090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Branch predictor suitable for multi-processing microprocessor' [patent_app_type] => utility [patent_app_number] => 09/775230 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3876 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877090.pdf [firstpage_image] =>[orig_patent_app_number] => 09775230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5848405 [patent_doc_number] => 20020133688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'SIMD/MIMD processing on a reconfigurable array' [patent_app_type] => new [patent_app_number] => 09/772591 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2367 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133688.pdf [firstpage_image] =>[orig_patent_app_number] => 09772591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6883309 [patent_doc_number] => 20010049781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Computer with high-speed context switching' [patent_app_type] => new [patent_app_number] => 09/768630 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18093 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049781.pdf [firstpage_image] =>[orig_patent_app_number] => 09768630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6659664 [patent_doc_number] => 20030079116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Facilitating value prediction to support speculative program execution' [patent_app_type] => new [patent_app_number] => 09/761217 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5850 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20030079116.pdf [firstpage_image] =>[orig_patent_app_number] => 09761217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 156216 [patent_doc_number] => 07681018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set' [patent_app_type] => utility [patent_app_number] => 09/760509 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10098 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681018.pdf [firstpage_image] =>[orig_patent_app_number] => 09760509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6894533 [patent_doc_number] => 20010016899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Data-processing device' [patent_app_type] => new [patent_app_number] => 09/760405 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4016 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016899.pdf [firstpage_image] =>[orig_patent_app_number] => 09760405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6900396 [patent_doc_number] => 20010010072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Instruction translator translating non-native instructions for a processor into native instructions therefor, instruction memory with such translator, and data processing apparatus using them' [patent_app_type] => new [patent_app_number] => 09/756863 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12696 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010072.pdf [firstpage_image] =>[orig_patent_app_number] => 09756863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 76395 [patent_doc_number] => 07757066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'System and method for executing variable latency load operations in a date processor' [patent_app_type] => utility [patent_app_number] => 09/751372 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5402 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757066.pdf [firstpage_image] =>[orig_patent_app_number] => 09751372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 623289 [patent_doc_number] => 07143268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Circuit and method for instruction compression and dispersal in wide-issue processors' [patent_app_type] => utility [patent_app_number] => 09/751674 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8580 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143268.pdf [firstpage_image] =>[orig_patent_app_number] => 09751674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 753064 [patent_doc_number] => 07028164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Instruction fetch apparatus for wide issue processors and method of operation' [patent_app_type] => utility [patent_app_number] => 09/751679 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028164.pdf [firstpage_image] =>[orig_patent_app_number] => 09751679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6648738 [patent_doc_number] => 20020087844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Apparatus and method for concealing switch latency' [patent_app_type] => new [patent_app_number] => 09/753766 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087844.pdf [firstpage_image] =>[orig_patent_app_number] => 09753766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6736979 [patent_doc_number] => 20030014614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Bypass circuitry for use in a pipelined processor' [patent_app_type] => new [patent_app_number] => 09/751377 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014614.pdf [firstpage_image] =>[orig_patent_app_number] => 09751377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5830497 [patent_doc_number] => 20020069351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Memory data access structure and method suitable for use in a processor' [patent_app_type] => new [patent_app_number] => 09/752122 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3793 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069351.pdf [firstpage_image] =>[orig_patent_app_number] => 09752122 [rel_patent_id] =>[rel_patent_doc_number] =>)