Search

Aimee J. Li

Supervisory Patent Examiner (ID: 5820, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2100, 2137, 2195
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 794311 [patent_doc_number] => 06983361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Apparatus and method for implementing switch instructions in an IA64 architecture' [patent_app_type] => utility [patent_app_number] => 09/671973 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3837 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983361.pdf [firstpage_image] =>[orig_patent_app_number] => 09671973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671973
Apparatus and method for implementing switch instructions in an IA64 architecture Sep 27, 2000 Issued
Array ( [id] => 513156 [patent_doc_number] => 07206925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Backing Register File for processors' [patent_app_type] => utility [patent_app_number] => 09/643895 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4528 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206925.pdf [firstpage_image] =>[orig_patent_app_number] => 09643895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643895
Backing Register File for processors Aug 17, 2000 Issued
09/640118 MACHANISM IN A MICROPROCESSOR FOR EXECUTING NATIVE INSTRUCTIONS DIRECTLY FROM MEMORY Aug 15, 2000 Abandoned
09/622117 Apparatus for and a method of executing instructions of a program Aug 10, 2000 Abandoned
Array ( [id] => 7608104 [patent_doc_number] => 07000096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Branch prediction circuits and methods and systems using the same' [patent_app_type] => utility [patent_app_number] => 09/631726 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 11 [patent_no_of_words] => 12539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000096.pdf [firstpage_image] =>[orig_patent_app_number] => 09631726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631726
Branch prediction circuits and methods and systems using the same Aug 2, 2000 Issued
Array ( [id] => 536414 [patent_doc_number] => 07191319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'System and method for preloading cache memory in response to an occurrence of a context switch' [patent_app_type] => utility [patent_app_number] => 09/631174 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6029 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191319.pdf [firstpage_image] =>[orig_patent_app_number] => 09631174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631174
System and method for preloading cache memory in response to an occurrence of a context switch Aug 1, 2000 Issued
Array ( [id] => 392844 [patent_doc_number] => 07302550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Stack of variable length operands and method for use' [patent_app_type] => utility [patent_app_number] => 10/030106 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1955 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302550.pdf [firstpage_image] =>[orig_patent_app_number] => 10030106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/030106
Stack of variable length operands and method for use Jul 16, 2000 Issued
Array ( [id] => 649063 [patent_doc_number] => 07120781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-10 [patent_title] => 'General purpose register file architecture for aligned simd' [patent_app_type] => utility [patent_app_number] => 09/608983 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2948 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120781.pdf [firstpage_image] =>[orig_patent_app_number] => 09608983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608983
General purpose register file architecture for aligned simd Jun 29, 2000 Issued
Array ( [id] => 662986 [patent_doc_number] => 07107437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-12 [patent_title] => 'Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)' [patent_app_type] => utility [patent_app_number] => 09/608852 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4048 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107437.pdf [firstpage_image] =>[orig_patent_app_number] => 09608852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608852
Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB) Jun 29, 2000 Issued
Array ( [id] => 1017235 [patent_doc_number] => 06895494 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Sub-pipelined and pipelined execution in a VLIW' [patent_app_type] => utility [patent_app_number] => 09/603226 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3133 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895494.pdf [firstpage_image] =>[orig_patent_app_number] => 09603226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603226
Sub-pipelined and pipelined execution in a VLIW Jun 25, 2000 Issued
Array ( [id] => 950100 [patent_doc_number] => 06963967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture' [patent_app_type] => utility [patent_app_number] => 09/588508 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9499 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963967.pdf [firstpage_image] =>[orig_patent_app_number] => 09588508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588508
System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture Jun 5, 2000 Issued
Array ( [id] => 7603595 [patent_doc_number] => 07117344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Processor execution, pipeline sharing instruction, and data source path' [patent_app_type] => utility [patent_app_number] => 09/586961 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 37290 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117344.pdf [firstpage_image] =>[orig_patent_app_number] => 09586961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586961
Processor execution, pipeline sharing instruction, and data source path Jun 4, 2000 Issued
Array ( [id] => 1143716 [patent_doc_number] => 06785802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/585076 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3475 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785802.pdf [firstpage_image] =>[orig_patent_app_number] => 09585076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585076
Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor May 31, 2000 Issued
Array ( [id] => 1271942 [patent_doc_number] => 06662293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Instruction dependency scoreboard with a hierarchical structure' [patent_app_type] => B1 [patent_app_number] => 09/577219 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662293.pdf [firstpage_image] =>[orig_patent_app_number] => 09577219 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577219
Instruction dependency scoreboard with a hierarchical structure May 22, 2000 Issued
Array ( [id] => 705175 [patent_doc_number] => 07069425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Real-time processor executing predetermined operation defined by program correctly at predetermined time' [patent_app_type] => utility [patent_app_number] => 09/573258 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 15518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069425.pdf [firstpage_image] =>[orig_patent_app_number] => 09573258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573258
Real-time processor executing predetermined operation defined by program correctly at predetermined time May 17, 2000 Issued
Array ( [id] => 955148 [patent_doc_number] => 06959379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'Multiple execution of instruction loops within a processor without accessing program memory' [patent_app_type] => utility [patent_app_number] => 09/562542 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/959/06959379.pdf [firstpage_image] =>[orig_patent_app_number] => 09562542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562542
Multiple execution of instruction loops within a processor without accessing program memory May 1, 2000 Issued
Array ( [id] => 350736 [patent_doc_number] => 07496734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'System and method for handling register dependency in a stack-based pipelined processor' [patent_app_type] => utility [patent_app_number] => 09/561241 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5588 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/496/07496734.pdf [firstpage_image] =>[orig_patent_app_number] => 09561241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561241
System and method for handling register dependency in a stack-based pipelined processor Apr 27, 2000 Issued
Array ( [id] => 659384 [patent_doc_number] => 07111156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method and apparatus for multi-thread accumulation buffering in a computation engine' [patent_app_type] => utility [patent_app_number] => 09/556473 [patent_app_country] => US [patent_app_date] => 2000-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19653 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111156.pdf [firstpage_image] =>[orig_patent_app_number] => 09556473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556473
Method and apparatus for multi-thread accumulation buffering in a computation engine Apr 20, 2000 Issued
Array ( [id] => 943576 [patent_doc_number] => 06971000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Use of software hint for branch prediction in the absence of hint bit in the branch instruction' [patent_app_type] => utility [patent_app_number] => 09/548469 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5546 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/971/06971000.pdf [firstpage_image] =>[orig_patent_app_number] => 09548469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548469
Use of software hint for branch prediction in the absence of hint bit in the branch instruction Apr 12, 2000 Issued
Array ( [id] => 302020 [patent_doc_number] => 07539849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive' [patent_app_type] => utility [patent_app_number] => 09/547288 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5243 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539849.pdf [firstpage_image] =>[orig_patent_app_number] => 09547288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547288
Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive Apr 10, 2000 Issued
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