Search

Aimee J. Li

Supervisory Patent Examiner (ID: 5820, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2100, 2137, 2195
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1229214 [patent_doc_number] => 06701424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method and apparatus for efficient loading and storing of vectors' [patent_app_type] => B1 [patent_app_number] => 09/545183 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 9495 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701424.pdf [firstpage_image] =>[orig_patent_app_number] => 09545183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545183
Method and apparatus for efficient loading and storing of vectors Apr 6, 2000 Issued
Array ( [id] => 706765 [patent_doc_number] => 07065632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and apparatus for speculatively forwarding storehit data in a hierarchical manner' [patent_app_type] => utility [patent_app_number] => 09/545040 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10333 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065632.pdf [firstpage_image] =>[orig_patent_app_number] => 09545040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545040
Method and apparatus for speculatively forwarding storehit data in a hierarchical manner Apr 6, 2000 Issued
Array ( [id] => 1214454 [patent_doc_number] => 06715065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Micro program control method and apparatus thereof having branch instructions' [patent_app_type] => B1 [patent_app_number] => 09/539898 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8113 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715065.pdf [firstpage_image] =>[orig_patent_app_number] => 09539898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539898
Micro program control method and apparatus thereof having branch instructions Mar 30, 2000 Issued
Array ( [id] => 1170172 [patent_doc_number] => 06766442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value' [patent_app_type] => B1 [patent_app_number] => 09/538992 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4674 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766442.pdf [firstpage_image] =>[orig_patent_app_number] => 09538992 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538992
Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value Mar 29, 2000 Issued
Array ( [id] => 995902 [patent_doc_number] => 06918028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-12 [patent_title] => 'Pipelined processor including a loosely coupled side pipe' [patent_app_type] => utility [patent_app_number] => 09/536656 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918028.pdf [firstpage_image] =>[orig_patent_app_number] => 09536656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536656
Pipelined processor including a loosely coupled side pipe Mar 27, 2000 Issued
Array ( [id] => 745001 [patent_doc_number] => 07036003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Instruction processing device and method for controlling branch instruction accompanied by mode change' [patent_app_type] => utility [patent_app_number] => 09/528714 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7325 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/036/07036003.pdf [firstpage_image] =>[orig_patent_app_number] => 09528714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528714
Instruction processing device and method for controlling branch instruction accompanied by mode change Mar 19, 2000 Issued
09/524178 Method and apparatus for loose register encoding within a pipelined processor Mar 12, 2000 Abandoned
09/524179 Method and apparatus for processor pipeline segmentation and re-assembly Mar 12, 2000 Abandoned
Array ( [id] => 7633018 [patent_doc_number] => 06658602 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Apparatus for detecting abnormal execution of program' [patent_app_type] => B1 [patent_app_number] => 09/522617 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2354 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658602.pdf [firstpage_image] =>[orig_patent_app_number] => 09522617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522617
Apparatus for detecting abnormal execution of program Mar 9, 2000 Issued
Array ( [id] => 1055826 [patent_doc_number] => 06859870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method and apparatus for compressing VLIW instruction and sharing subinstructions' [patent_app_type] => utility [patent_app_number] => 09/519695 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6154 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859870.pdf [firstpage_image] =>[orig_patent_app_number] => 09519695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519695
Method and apparatus for compressing VLIW instruction and sharing subinstructions Mar 6, 2000 Issued
Array ( [id] => 1197025 [patent_doc_number] => 06732260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Presbyopic branch target prefetch method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/518939 [patent_app_country] => US [patent_app_date] => 2000-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5011 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732260.pdf [firstpage_image] =>[orig_patent_app_number] => 09518939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/518939
Presbyopic branch target prefetch method and apparatus Mar 5, 2000 Issued
Array ( [id] => 1143700 [patent_doc_number] => 06785799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Multiprocessor with asynchronous pipeline processing of instructions, and control method thereof' [patent_app_type] => B1 [patent_app_number] => 09/514204 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10949 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785799.pdf [firstpage_image] =>[orig_patent_app_number] => 09514204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514204
Multiprocessor with asynchronous pipeline processing of instructions, and control method thereof Feb 24, 2000 Issued
Array ( [id] => 7626819 [patent_doc_number] => 06807625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions' [patent_app_type] => B1 [patent_app_number] => 09/507032 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 3 [patent_no_of_words] => 2219 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807625.pdf [firstpage_image] =>[orig_patent_app_number] => 09507032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507032
Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions Feb 17, 2000 Issued
Array ( [id] => 7629979 [patent_doc_number] => 06636960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method and apparatus for resteering failing speculation check instructions' [patent_app_type] => B1 [patent_app_number] => 09/505093 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636960.pdf [firstpage_image] =>[orig_patent_app_number] => 09505093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505093
Method and apparatus for resteering failing speculation check instructions Feb 15, 2000 Issued
Array ( [id] => 641178 [patent_doc_number] => 07127595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method and system for configuring to a desired order the order of a data array' [patent_app_type] => utility [patent_app_number] => 09/505414 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 2591 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/127/07127595.pdf [firstpage_image] =>[orig_patent_app_number] => 09505414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505414
Method and system for configuring to a desired order the order of a data array Feb 15, 2000 Issued
Array ( [id] => 1260486 [patent_doc_number] => 06668316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method and apparatus for conflict-free execution of integer and floating-point operations with a common register file' [patent_app_type] => B1 [patent_app_number] => 09/504966 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6998 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668316.pdf [firstpage_image] =>[orig_patent_app_number] => 09504966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504966
Method and apparatus for conflict-free execution of integer and floating-point operations with a common register file Feb 14, 2000 Issued
Array ( [id] => 890555 [patent_doc_number] => 07353368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support' [patent_app_type] => utility [patent_app_number] => 09/505949 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3742 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353368.pdf [firstpage_image] =>[orig_patent_app_number] => 09505949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505949
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support Feb 14, 2000 Issued
Array ( [id] => 940476 [patent_doc_number] => 06973562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Establishing an operating mode in a processor' [patent_app_type] => utility [patent_app_number] => 09/483101 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11423 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973562.pdf [firstpage_image] =>[orig_patent_app_number] => 09483101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483101
Establishing an operating mode in a processor Jan 13, 2000 Issued
Array ( [id] => 1279621 [patent_doc_number] => 06654873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Processor apparatus and integrated circuit employing prefetching and predecoding' [patent_app_type] => B2 [patent_app_number] => 09/479570 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3492 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654873.pdf [firstpage_image] =>[orig_patent_app_number] => 09479570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479570
Processor apparatus and integrated circuit employing prefetching and predecoding Jan 6, 2000 Issued
Array ( [id] => 1429370 [patent_doc_number] => 06530010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Multiplexer reconfigurable image processing peripheral having for loop control' [patent_app_type] => B1 [patent_app_number] => 09/475928 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 14837 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1033 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530010.pdf [firstpage_image] =>[orig_patent_app_number] => 09475928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475928
Multiplexer reconfigurable image processing peripheral having for loop control Dec 29, 1999 Issued
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