Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10672916 [patent_doc_number] => 20160019061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'MANAGING DATAFLOW EXECUTION OF LOOP INSTRUCTIONS BY OUT-OF-ORDER PROCESSORS (OOPs), AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/485899 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485899 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485899
MANAGING DATAFLOW EXECUTION OF LOOP INSTRUCTIONS BY OUT-OF-ORDER PROCESSORS (OOPs), AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA Sep 14, 2014 Abandoned
Array ( [id] => 9834463 [patent_doc_number] => 08943298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Meta predictor restoration upon detecting misprediction' [patent_app_type] => utility [patent_app_number] => 14/064900 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3613 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064900
Meta predictor restoration upon detecting misprediction Oct 27, 2013 Issued
Array ( [id] => 10215767 [patent_doc_number] => 20150100759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'PIPELINED FINITE STATE MACHINE' [patent_app_type] => utility [patent_app_number] => 14/047402 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047402
PIPELINED FINITE STATE MACHINE Oct 6, 2013 Abandoned
Array ( [id] => 9264799 [patent_doc_number] => 20130346728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions' [patent_app_type] => utility [patent_app_number] => 14/012344 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14012344 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/012344
Optimizing performance of instructions based on sequence detection or information associated with the instructions Aug 27, 2013 Issued
Array ( [id] => 9765821 [patent_doc_number] => 08850169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Disabling threads in multithread environment' [patent_app_type] => utility [patent_app_number] => 13/932889 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932889
Disabling threads in multithread environment Jun 30, 2013 Issued
Array ( [id] => 9123762 [patent_doc_number] => 20130290684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'DATA PACKET ARITHMETIC LOGIC DEVICES AND MEHTODS' [patent_app_type] => utility [patent_app_number] => 13/927036 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8566 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927036 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927036
Data packet arithmetic logic devices and methods Jun 24, 2013 Issued
Array ( [id] => 9707320 [patent_doc_number] => 08832413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Processing system with interspersed processors and communication elements having improved wormhole routing' [patent_app_type] => utility [patent_app_number] => 13/904359 [patent_app_country] => US [patent_app_date] => 2013-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 21156 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13904359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/904359
Processing system with interspersed processors and communication elements having improved wormhole routing May 28, 2013 Issued
Array ( [id] => 9044111 [patent_doc_number] => 20130246749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'DATA PROCESSOR TO PROCESS DATA' [patent_app_type] => utility [patent_app_number] => 13/861798 [patent_app_country] => US [patent_app_date] => 2013-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/861798
Data processor including an operation unit to execute operations in parallel Apr 11, 2013 Issued
Array ( [id] => 9688219 [patent_doc_number] => 20140244984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'ELIGIBLE STORE MAPS FOR STORE-TO-LOAD FORWARDING' [patent_app_type] => utility [patent_app_number] => 13/777876 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8835 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777876 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777876
ELIGIBLE STORE MAPS FOR STORE-TO-LOAD FORWARDING Feb 25, 2013 Abandoned
Array ( [id] => 9532520 [patent_doc_number] => 08756406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-17 [patent_title] => 'Method and apparatus for programmable coupling between CPU and co-processor' [patent_app_type] => utility [patent_app_number] => 13/739512 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4622 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739512
Method and apparatus for programmable coupling between CPU and co-processor Jan 10, 2013 Issued
Array ( [id] => 8850691 [patent_doc_number] => 20130140366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 13/734801 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8276 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734801 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734801
Methods and apparatus for matrix decompositions in programmable logic devices Jan 3, 2013 Issued
Array ( [id] => 9834678 [patent_doc_number] => 08943512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Systems and methods for facilitating virtualization of a heterogeneous processor pool' [patent_app_type] => utility [patent_app_number] => 13/722216 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722216 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722216
Systems and methods for facilitating virtualization of a heterogeneous processor pool Dec 19, 2012 Issued
Array ( [id] => 8650567 [patent_doc_number] => 20130036297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION' [patent_app_type] => utility [patent_app_number] => 13/647153 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13647153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/647153
Meta predictor restoration upon detecting misprediction Oct 7, 2012 Issued
Array ( [id] => 8407846 [patent_doc_number] => 20120239915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'Interrupt Handling' [patent_app_type] => utility [patent_app_number] => 13/479788 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5526 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479788 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479788
Interrupt handling May 23, 2012 Issued
Array ( [id] => 10890609 [patent_doc_number] => 08914622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Processor testing' [patent_app_type] => utility [patent_app_number] => 13/460413 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7323 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460413 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460413
Processor testing Apr 29, 2012 Issued
Array ( [id] => 8326048 [patent_doc_number] => 20120198453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'VIRTUALIZATION OF STORAGE BUFFERS USED BY ASYNCHRONOUS PROCESSES' [patent_app_type] => utility [patent_app_number] => 13/446862 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14392 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446862
Virtualization of storage buffers used by asynchronous processes Apr 12, 2012 Issued
Array ( [id] => 8455022 [patent_doc_number] => 20120265967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS' [patent_app_type] => utility [patent_app_number] => 13/425808 [patent_app_country] => US [patent_app_date] => 2012-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13425808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/425808
Implementing instruction set architectures with non-contiguous register file specifiers Mar 20, 2012 Issued
Array ( [id] => 8222906 [patent_doc_number] => 20120137110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'HARDWARE DEVICE FOR PROCESSING THE TASKS OF AN ALGORITHM IN PARALLEL' [patent_app_type] => utility [patent_app_number] => 13/365376 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365376 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/365376
Hardware device for processing the tasks of an algorithm in parallel Feb 2, 2012 Issued
Array ( [id] => 8162590 [patent_doc_number] => 20120102299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'STALL PROPAGATION IN A PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATON ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/341252 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21161 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102299.pdf [firstpage_image] =>[orig_patent_app_number] => 13341252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/341252
Stall propagation in a processing system with interspersed processors and communicaton elements Dec 29, 2011 Issued
Array ( [id] => 8899437 [patent_doc_number] => 08478971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Multithread handling' [patent_app_type] => utility [patent_app_number] => 13/330305 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5845 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330305
Multithread handling Dec 18, 2011 Issued
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