Aimee J. Li

Array ( [id] => 8201771 [patent_doc_number] => 20120124332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'VECTOR PROCESSING CIRCUIT, COMMAND ISSUANCE CONTROL METHOD, AND PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/279482 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124332.pdf [firstpage_image] =>[orig_patent_app_number] => 13279482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7819859 [patent_doc_number] => 20120066479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHODS AND APPARATUS FOR HANDLING SWITCHING AMONG THREADS WITHIN A MULTITHREAD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/247030 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066479.pdf [firstpage_image] =>[orig_patent_app_number] => 13247030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7582261 [patent_doc_number] => 20110296144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION' [patent_app_type] => utility [patent_app_number] => 13/205552 [patent_app_country] => US [patent_app_date] => 2011-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6862 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296144.pdf [firstpage_image] =>[orig_patent_app_number] => 13205552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8626954 [patent_doc_number] => 08359458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Methods and apparatus for matrix decompositions in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 13/179850 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13179850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8804890 [patent_doc_number] => 08443173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method for instructing a data processor to process data' [patent_app_type] => utility [patent_app_number] => 13/153035 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 17544 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10879356 [patent_doc_number] => 08904154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Execution migration' [patent_app_type] => utility [patent_app_number] => 13/087712 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9173 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13087712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6052229 [patent_doc_number] => 20110208950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS' [patent_app_type] => utility [patent_app_number] => 13/053000 [patent_app_country] => US [patent_app_date] => 2011-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 42235 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20110208950.pdf [firstpage_image] =>[orig_patent_app_number] => 13053000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8912368 [patent_doc_number] => 08484444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Methods and apparatus for attaching application specific functions within an array processor' [patent_app_type] => utility [patent_app_number] => 13/037824 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5948551 [patent_doc_number] => 20110107062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Interrupt Handling' [patent_app_type] => utility [patent_app_number] => 12/987716 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107062.pdf [firstpage_image] =>[orig_patent_app_number] => 12987716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9665818 [patent_doc_number] => 08812826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Processor testing' [patent_app_type] => utility [patent_app_number] => 12/908370 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7326 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12908370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5956766 [patent_doc_number] => 20110035567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'ACTUAL INSTRUCTION AND ACTUAL-FAULT INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/907490 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 39639 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035567.pdf [firstpage_image] =>[orig_patent_app_number] => 12907490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6031404 [patent_doc_number] => 20110055497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing' [patent_app_type] => utility [patent_app_number] => 12/875268 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8841 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055497.pdf [firstpage_image] =>[orig_patent_app_number] => 12875268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5996274 [patent_doc_number] => 20110016288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Serial Flash Memory and Address Transmission Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/837823 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20110016288.pdf [firstpage_image] =>[orig_patent_app_number] => 12837823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8001159 [patent_doc_number] => 08082427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Multithread handling' [patent_app_type] => utility [patent_app_number] => 12/831984 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082427.pdf [firstpage_image] =>[orig_patent_app_number] => 12831984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4606353 [patent_doc_number] => 07987339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Processing system with interspersed processors and dynamic pathway creation' [patent_app_type] => utility [patent_app_number] => 12/827416 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 21127 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987339.pdf [firstpage_image] =>[orig_patent_app_number] => 12827416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6633874 [patent_doc_number] => 20100325386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/821732 [patent_app_country] => US [patent_app_date] => 2010-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 26253 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325386.pdf [firstpage_image] =>[orig_patent_app_number] => 12821732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9130180 [patent_doc_number] => 08578136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Apparatus and method for mapping architectural registers to physical registers' [patent_app_type] => utility [patent_app_number] => 12/801576 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6849 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12801576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6636324 [patent_doc_number] => 20100325631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'METHOD AND APPARATUS FOR INCREASING LOAD BANDWIDTH' [patent_app_type] => utility [patent_app_number] => 12/816297 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325631.pdf [firstpage_image] =>[orig_patent_app_number] => 12816297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9358552 [patent_doc_number] => 08677106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Unanimous branch instructions in a parallel thread processor' [patent_app_type] => utility [patent_app_number] => 12/815226 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12815226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9251855 [patent_doc_number] => 08615646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Unanimous branch instructions in a parallel thread processor' [patent_app_type] => utility [patent_app_number] => 12/815201 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10276 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12815201 [rel_patent_id] =>[rel_patent_doc_number] =>)