
Aimee J. Li
Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2195, 2137, 2100 |
| Total Applications | 539 |
| Issued Applications | 378 |
| Pending Applications | 20 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5996285
[patent_doc_number] => 20110016291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-20
[patent_title] => 'Serial Memory Interface for Extended Address Space'
[patent_app_type] => utility
[patent_app_number] => 12/813395
[patent_app_country] => US
[patent_app_date] => 2010-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5947
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20110016291.pdf
[firstpage_image] =>[orig_patent_app_number] => 12813395
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/813395 | Serial memory interface for extended address space | Jun 9, 2010 | Issued |
Array
(
[id] => 10867128
[patent_doc_number] => 08892853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-18
[patent_title] => 'Hardware to support looping code in an image processing system'
[patent_app_type] => utility
[patent_app_number] => 12/797689
[patent_app_country] => US
[patent_app_date] => 2010-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5989
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797689
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/797689 | Hardware to support looping code in an image processing system | Jun 9, 2010 | Issued |
Array
(
[id] => 7658392
[patent_doc_number] => 20110307661
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-15
[patent_title] => 'MULTI-PROCESSOR CHIP WITH SHARED FPGA EXECUTION UNIT AND A DESIGN STRUCTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/796990
[patent_app_country] => US
[patent_app_date] => 2010-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6350
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0307/20110307661.pdf
[firstpage_image] =>[orig_patent_app_number] => 12796990
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/796990 | MULTI-PROCESSOR CHIP WITH SHARED FPGA EXECUTION UNIT AND A DESIGN STRUCTURE THEREOF | Jun 8, 2010 | Abandoned |
Array
(
[id] => 7653125
[patent_doc_number] => 20110302394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-08
[patent_title] => 'SYSTEM AND METHOD FOR PROCESSING REGULAR EXPRESSIONS USING SIMD AND PARALLEL STREAMS'
[patent_app_type] => utility
[patent_app_number] => 12/795874
[patent_app_country] => US
[patent_app_date] => 2010-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4847
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0302/20110302394.pdf
[firstpage_image] =>[orig_patent_app_number] => 12795874
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/795874 | SYSTEM AND METHOD FOR PROCESSING REGULAR EXPRESSIONS USING SIMD AND PARALLEL STREAMS | Jun 7, 2010 | Abandoned |
Array
(
[id] => 6616359
[patent_doc_number] => 20100293356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-18
[patent_title] => 'METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 12/785868
[patent_app_country] => US
[patent_app_date] => 2010-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 9628
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0293/20100293356.pdf
[firstpage_image] =>[orig_patent_app_number] => 12785868
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/785868 | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture | May 23, 2010 | Issued |
Array
(
[id] => 4626761
[patent_doc_number] => 08006072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Reducing data hazards in pipelined processors to provide high processor utilization'
[patent_app_type] => utility
[patent_app_number] => 12/782474
[patent_app_country] => US
[patent_app_date] => 2010-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 7843
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/006/08006072.pdf
[firstpage_image] =>[orig_patent_app_number] => 12782474
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/782474 | Reducing data hazards in pipelined processors to provide high processor utilization | May 17, 2010 | Issued |
Array
(
[id] => 6651826
[patent_doc_number] => 20100229020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SELECTIVE DATA TRANSFER THROUGH COMMUNICATON ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 12/781422
[patent_app_country] => US
[patent_app_date] => 2010-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 21126
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20100229020.pdf
[firstpage_image] =>[orig_patent_app_number] => 12781422
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/781422 | Processing system with interspersed processors using selective data transfer through communication elements | May 16, 2010 | Issued |
Array
(
[id] => 4606352
[patent_doc_number] => 07987338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Processing system with interspersed processors using shared memory of communication elements'
[patent_app_type] => utility
[patent_app_number] => 12/781314
[patent_app_country] => US
[patent_app_date] => 2010-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 21126
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/987/07987338.pdf
[firstpage_image] =>[orig_patent_app_number] => 12781314
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/781314 | Processing system with interspersed processors using shared memory of communication elements | May 16, 2010 | Issued |
Array
(
[id] => 6523514
[patent_doc_number] => 20100211762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-19
[patent_title] => 'Mechanism for Efficient Implementation of Software Pipelined Loops in VLIW Processors'
[patent_app_type] => utility
[patent_app_number] => 12/708288
[patent_app_country] => US
[patent_app_date] => 2010-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7132
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20100211762.pdf
[firstpage_image] =>[orig_patent_app_number] => 12708288
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/708288 | Mechanism for efficient implementation of software pipelined loops in VLIW processors | Feb 17, 2010 | Issued |
Array
(
[id] => 6067476
[patent_doc_number] => 20110202748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'LOAD PAIR DISJOINT FACILITY AND INSTRUCTION THEREFORE'
[patent_app_type] => utility
[patent_app_number] => 12/708284
[patent_app_country] => US
[patent_app_date] => 2010-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 22832
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20110202748.pdf
[firstpage_image] =>[orig_patent_app_number] => 12708284
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/708284 | Load pair disjoint facility and instruction therefore | Feb 17, 2010 | Issued |
Array
(
[id] => 6067472
[patent_doc_number] => 20110202745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'METHOD AND APPARATUS FOR COMPUTING MASSIVE SPATIO-TEMPORAL CORRELATIONS USING A HYBRID CPU-GPU APPROACH'
[patent_app_type] => utility
[patent_app_number] => 12/707198
[patent_app_country] => US
[patent_app_date] => 2010-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5068
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20110202745.pdf
[firstpage_image] =>[orig_patent_app_number] => 12707198
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/707198 | Method and apparatus for computing massive spatio-temporal correlations using a hybrid CPU-GPU approach | Feb 16, 2010 | Issued |
Array
(
[id] => 6067474
[patent_doc_number] => 20110202747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'INSTRUCTION LENGTH BASED CRACKING FOR INSTRUCTION OF VARIABLE LENGTH STORAGE OPERANDS'
[patent_app_type] => utility
[patent_app_number] => 12/707163
[patent_app_country] => US
[patent_app_date] => 2010-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20110202747.pdf
[firstpage_image] =>[orig_patent_app_number] => 12707163
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/707163 | Instruction length based cracking for instruction of variable length storage operands | Feb 16, 2010 | Issued |
Array
(
[id] => 6523465
[patent_doc_number] => 20100211759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-19
[patent_title] => 'APPARATUS AND METHOD FOR GENERATING VLIW, AND PROCESSOR AND METHOD FOR PROCESSING VLIW'
[patent_app_type] => utility
[patent_app_number] => 12/706006
[patent_app_country] => US
[patent_app_date] => 2010-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4397
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20100211759.pdf
[firstpage_image] =>[orig_patent_app_number] => 12706006
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/706006 | Apparatus and method for generating VLIW, and processor and method for processing VLIW | Feb 15, 2010 | Issued |
Array
(
[id] => 6554661
[patent_doc_number] => 20100205410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'Data Processing'
[patent_app_type] => utility
[patent_app_number] => 12/705234
[patent_app_country] => US
[patent_app_date] => 2010-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9034
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20100205410.pdf
[firstpage_image] =>[orig_patent_app_number] => 12705234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/705234 | Apparatus and method for temporarily freeing up resources in a computer | Feb 11, 2010 | Issued |
Array
(
[id] => 5981591
[patent_doc_number] => 20110072242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-24
[patent_title] => 'CONFIGURABLE PROCESSING APPARATUS AND SYSTEM THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/701594
[patent_app_country] => US
[patent_app_date] => 2010-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 12387
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20110072242.pdf
[firstpage_image] =>[orig_patent_app_number] => 12701594
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/701594 | Configurable processing apparatus and system thereof | Feb 6, 2010 | Issued |
Array
(
[id] => 9143419
[patent_doc_number] => 08583901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-12
[patent_title] => 'Register renaming system using multi-bank physical register mapping table and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/700638
[patent_app_country] => US
[patent_app_date] => 2010-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16395
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700638
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/700638 | Register renaming system using multi-bank physical register mapping table and method thereof | Feb 3, 2010 | Issued |
Array
(
[id] => 9143419
[patent_doc_number] => 08583901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-12
[patent_title] => 'Register renaming system using multi-bank physical register mapping table and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/700638
[patent_app_country] => US
[patent_app_date] => 2010-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16395
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700638
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/700638 | Register renaming system using multi-bank physical register mapping table and method thereof | Feb 3, 2010 | Issued |
Array
(
[id] => 6006058
[patent_doc_number] => 20110119468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-19
[patent_title] => 'MECHANISM OF SUPPORTING SUB-COMMUNICATOR COLLECTIVES WITH O(64) COUNTERS AS OPPOSED TO ONE COUNTER FOR EACH SUB-COMMUNICATOR'
[patent_app_type] => utility
[patent_app_number] => 12/697164
[patent_app_country] => US
[patent_app_date] => 2010-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4615
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20110119468.pdf
[firstpage_image] =>[orig_patent_app_number] => 12697164
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/697164 | Mechanism of supporting sub-communicator collectives with O(64) counters as opposed to one counter for each sub-communicator | Jan 28, 2010 | Issued |
Array
(
[id] => 6277694
[patent_doc_number] => 20100118852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-13
[patent_title] => 'System and Method of Processing Data Using Scalar/Vector Instructions'
[patent_app_type] => utility
[patent_app_number] => 12/690213
[patent_app_country] => US
[patent_app_date] => 2010-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7978
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20100118852.pdf
[firstpage_image] =>[orig_patent_app_number] => 12690213
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/690213 | System and method of processing data using scalar/vector instructions | Jan 19, 2010 | Issued |
Array
(
[id] => 6463764
[patent_doc_number] => 20100146244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-10
[patent_title] => 'METHOD FOR INSTRUCTING A DATA PROCESSOR TO PROCESS DATA'
[patent_app_type] => utility
[patent_app_number] => 12/632532
[patent_app_country] => US
[patent_app_date] => 2009-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17395
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20100146244.pdf
[firstpage_image] =>[orig_patent_app_number] => 12632532
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/632532 | Method for instructing a data processor to process data | Dec 6, 2009 | Issued |