Aimee J. Li

Array ( [id] => 6312543 [patent_doc_number] => 20100070738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'FLEXIBLE RESULTS PIPELINE FOR PROCESSING ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/621400 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2739 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070738.pdf [firstpage_image] =>[orig_patent_app_number] => 12621400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8033577 [patent_doc_number] => 08145884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor' [patent_app_type] => utility [patent_app_number] => 12/605201 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9075 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/145/08145884.pdf [firstpage_image] =>[orig_patent_app_number] => 12605201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8861475 [patent_doc_number] => 08464029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Out-of-order execution microprocessor with reduced store collision load replay reduction' [patent_app_type] => utility [patent_app_number] => 12/604930 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 12953 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12604930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6645828 [patent_doc_number] => 20100174765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'PERFORMING VARIABLE AND/OR BITWISE SHIFT OPERATION FOR A SHIFT INSTRUCTION THAT DOES NOT PROVIDE A VARIABLE OR BITWISE SHIFT OPTION' [patent_app_type] => utility [patent_app_number] => 12/573876 [patent_app_country] => US [patent_app_date] => 2009-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5540 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174765.pdf [firstpage_image] =>[orig_patent_app_number] => 12573876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787030 [patent_doc_number] => 08433884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Multiprocessor' [patent_app_type] => utility [patent_app_number] => 12/674052 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9945 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12674052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532563 [patent_doc_number] => 07844797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 12/436607 [patent_app_country] => US [patent_app_date] => 2009-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11073 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 460 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844797.pdf [firstpage_image] =>[orig_patent_app_number] => 12436607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6535536 [patent_doc_number] => 20100262964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Virtual Machine Packing Method Using Scarcity' [patent_app_type] => utility [patent_app_number] => 12/422123 [patent_app_country] => US [patent_app_date] => 2009-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262964.pdf [firstpage_image] =>[orig_patent_app_number] => 12422123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8873146 [patent_doc_number] => 08468535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-18 [patent_title] => 'Automated system and method to provision and allocate hosting resources' [patent_app_type] => utility [patent_app_number] => 12/421605 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 35 [patent_no_of_words] => 30458 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12421605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8849517 [patent_doc_number] => 08458717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'System and method for automated criteria based deployment of virtual machines across a grid of hosting resources' [patent_app_type] => utility [patent_app_number] => 12/421599 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 35 [patent_no_of_words] => 30457 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12421599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8752332 [patent_doc_number] => 08418176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-09 [patent_title] => 'System and method for adapting virtual machine configurations for hosting across different hosting systems' [patent_app_type] => utility [patent_app_number] => 12/421610 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 24259 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12421610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8401371 [patent_doc_number] => 08271765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Managing instructions for more efficient load/store unit usage' [patent_app_type] => utility [patent_app_number] => 12/420143 [patent_app_country] => US [patent_app_date] => 2009-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12420143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6533396 [patent_doc_number] => 20100262811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'DEBUG SIGNALING IN A MULTIPLE PROCESSOR DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/420521 [patent_app_country] => US [patent_app_date] => 2009-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262811.pdf [firstpage_image] =>[orig_patent_app_number] => 12420521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8260013 [patent_doc_number] => 08209525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Method and apparatus for executing program code' [patent_app_type] => utility [patent_app_number] => 12/419629 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 29936 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12419629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8623239 [patent_doc_number] => 08356159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Break, pre-break, and remaining instructions for processing vectors' [patent_app_type] => utility [patent_app_number] => 12/419644 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 30464 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12419644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8149268 [patent_doc_number] => 08166284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Information processing device' [patent_app_type] => utility [patent_app_number] => 12/420051 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166284.pdf [firstpage_image] =>[orig_patent_app_number] => 12420051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220059 [patent_doc_number] => 08195923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Methods and mechanisms to support multiple features for a number of opcodes' [patent_app_type] => utility [patent_app_number] => 12/420054 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195923.pdf [firstpage_image] =>[orig_patent_app_number] => 12420054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5497501 [patent_doc_number] => 20090265529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Processor apparatus and method of processing multiple data by single instructions' [patent_app_type] => utility [patent_app_number] => 12/385406 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10905 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265529.pdf [firstpage_image] =>[orig_patent_app_number] => 12385406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6280892 [patent_doc_number] => 20100257340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'System and Method for Group Formation with Multiple Taken Branches Per Group' [patent_app_type] => utility [patent_app_number] => 12/417798 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257340.pdf [firstpage_image] =>[orig_patent_app_number] => 12417798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7557536 [patent_doc_number] => 08069446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Parallel programming and execution systems and techniques' [patent_app_type] => utility [patent_app_number] => 12/418452 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069446.pdf [firstpage_image] =>[orig_patent_app_number] => 12418452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7798398 [patent_doc_number] => 08127116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Dependency matrix with reduced area and power consumption' [patent_app_type] => utility [patent_app_number] => 12/417768 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127116.pdf [firstpage_image] =>[orig_patent_app_number] => 12417768 [rel_patent_id] =>[rel_patent_doc_number] =>)