Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8183432 [patent_doc_number] => 08181175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'Accounting for resource usage time by a virtual machine' [patent_app_type] => utility [patent_app_number] => 12/236196 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3608 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181175.pdf [firstpage_image] =>[orig_patent_app_number] => 12236196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236196
Accounting for resource usage time by a virtual machine Sep 22, 2008 Issued
Array ( [id] => 8633070 [patent_doc_number] => 08365169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'Migrating a virtual machine across processing cells connected to an interconnect that provides data communication without cache coherency support' [patent_app_type] => utility [patent_app_number] => 12/236244 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4316 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12236244 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236244
Migrating a virtual machine across processing cells connected to an interconnect that provides data communication without cache coherency support Sep 22, 2008 Issued
Array ( [id] => 8558360 [patent_doc_number] => 08332847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-11 [patent_title] => 'Validating manual virtual machine migration' [patent_app_type] => utility [patent_app_number] => 12/236271 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5463 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12236271 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236271
Validating manual virtual machine migration Sep 22, 2008 Issued
Array ( [id] => 116482 [patent_doc_number] => 07721070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => utility [patent_app_number] => 12/235215 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 32645 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721070.pdf [firstpage_image] =>[orig_patent_app_number] => 12235215 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/235215
High-performance, superscalar-based computer system with out-of-order instruction execution Sep 21, 2008 Issued
Array ( [id] => 9314910 [patent_doc_number] => 08656145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Methods and systems for allocating interrupts in a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 12/233688 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6390 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12233688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233688
Methods and systems for allocating interrupts in a multithreaded processor Sep 18, 2008 Issued
Array ( [id] => 4961646 [patent_doc_number] => 20080276071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'REDUCING THE FETCH TIME OF TARGET INSTRUCTIONS OF A PREDICTED TAKEN BRANCH INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 12/176386 [patent_app_country] => US [patent_app_date] => 2008-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7686 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276071.pdf [firstpage_image] =>[orig_patent_app_number] => 12176386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176386
REDUCING THE FETCH TIME OF TARGET INSTRUCTIONS OF A PREDICTED TAKEN BRANCH INSTRUCTION Jul 19, 2008 Abandoned
Array ( [id] => 106834 [patent_doc_number] => 07730283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Simple load and store disambiguation and scheduling at predecode' [patent_app_type] => utility [patent_app_number] => 12/174529 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 17545 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730283.pdf [firstpage_image] =>[orig_patent_app_number] => 12174529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174529
Simple load and store disambiguation and scheduling at predecode Jul 15, 2008 Issued
Array ( [id] => 4961650 [patent_doc_number] => 20080276075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE' [patent_app_type] => utility [patent_app_number] => 12/174538 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276075.pdf [firstpage_image] =>[orig_patent_app_number] => 12174538 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174538
SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE Jul 15, 2008 Abandoned
Array ( [id] => 8183073 [patent_doc_number] => 08181003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Instruction set design, control and communication in programmable microprocessor cores and the like' [patent_app_type] => utility [patent_app_number] => 12/156007 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6058 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181003.pdf [firstpage_image] =>[orig_patent_app_number] => 12156007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/156007
Instruction set design, control and communication in programmable microprocessor cores and the like May 28, 2008 Issued
Array ( [id] => 8354992 [patent_doc_number] => 08250338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing' [patent_app_type] => utility [patent_app_number] => 12/129042 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12129042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129042
Broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing May 28, 2008 Issued
Array ( [id] => 8655430 [patent_doc_number] => 08375197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Performing an allreduce operation on a plurality of compute nodes of a parallel computer' [patent_app_type] => utility [patent_app_number] => 12/124763 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12208 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12124763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124763
Performing an allreduce operation on a plurality of compute nodes of a parallel computer May 20, 2008 Issued
Array ( [id] => 8912364 [patent_doc_number] => 08484440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Performing an allreduce operation on a plurality of compute nodes of a parallel computer' [patent_app_type] => utility [patent_app_number] => 12/124745 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12124745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124745
Performing an allreduce operation on a plurality of compute nodes of a parallel computer May 20, 2008 Issued
Array ( [id] => 8120101 [patent_doc_number] => 08161268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Performing an allreduce operation on a plurality of compute nodes of a parallel computer' [patent_app_type] => utility [patent_app_number] => 12/124756 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 13615 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161268.pdf [firstpage_image] =>[orig_patent_app_number] => 12124756 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124756
Performing an allreduce operation on a plurality of compute nodes of a parallel computer May 20, 2008 Issued
Array ( [id] => 9348091 [patent_doc_number] => 08667254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Method and apparatus for processing data in an embedded system' [patent_app_type] => utility [patent_app_number] => 12/121614 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12121614 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121614
Method and apparatus for processing data in an embedded system May 14, 2008 Issued
Array ( [id] => 4731021 [patent_doc_number] => 20080209437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'MULTITHREADED MULTICORE UNIPROCESSOR AND A HETEROGENEOUS MULTIPROCESSOR INCORPORATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/118958 [patent_app_country] => US [patent_app_date] => 2008-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4670 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209437.pdf [firstpage_image] =>[orig_patent_app_number] => 12118958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/118958
MULTITHREADED MULTICORE UNIPROCESSOR AND A HETEROGENEOUS MULTIPROCESSOR INCORPORATING THE SAME May 11, 2008 Abandoned
Array ( [id] => 5467472 [patent_doc_number] => 20090327672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SECURED PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 12/108443 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5808 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327672.pdf [firstpage_image] =>[orig_patent_app_number] => 12108443 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108443
Secured processing unit Apr 22, 2008 Issued
Array ( [id] => 4614152 [patent_doc_number] => 07996657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Reconfigurable computing circuit' [patent_app_type] => utility [patent_app_number] => 12/105551 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9785 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996657.pdf [firstpage_image] =>[orig_patent_app_number] => 12105551 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105551
Reconfigurable computing circuit Apr 17, 2008 Issued
Array ( [id] => 4956497 [patent_doc_number] => 20080189521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Speculative Instruction Issue in a Simultaneously Multithreaded Processor' [patent_app_type] => utility [patent_app_number] => 12/105091 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3634 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189521.pdf [firstpage_image] =>[orig_patent_app_number] => 12105091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105091
Speculative instruction issue in a simultaneously multithreaded processor Apr 16, 2008 Issued
Array ( [id] => 8247266 [patent_doc_number] => 08205209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Selecting a number of processing resources to run an application effectively while saving power' [patent_app_type] => utility [patent_app_number] => 12/050336 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6998 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205209.pdf [firstpage_image] =>[orig_patent_app_number] => 12050336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050336
Selecting a number of processing resources to run an application effectively while saving power Mar 17, 2008 Issued
Array ( [id] => 8149461 [patent_doc_number] => 08166477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'System and method for restoration of an execution environment from hibernation into a virtual or physical machine' [patent_app_type] => utility [patent_app_number] => 12/050409 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5678 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166477.pdf [firstpage_image] =>[orig_patent_app_number] => 12050409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050409
System and method for restoration of an execution environment from hibernation into a virtual or physical machine Mar 17, 2008 Issued
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