
Aiqun Li
Examiner (ID: 3811, Phone: (571)270-7736 , Office: P/1768 )
| Most Active Art Unit | 1768 |
| Art Unit(s) | 1796, 1763, 1768, 1766 |
| Total Applications | 951 |
| Issued Applications | 565 |
| Pending Applications | 85 |
| Abandoned Applications | 319 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7053942
[patent_doc_number] => 20050275114
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Semiconductor device and semiconductor apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/975385
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6519
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0275/20050275114.pdf
[firstpage_image] =>[orig_patent_app_number] => 10975385
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/975385 | Semiconductor device and semiconductor apparatus | Oct 28, 2004 | Issued |
Array
(
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[patent_doc_number] => 07253507
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[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
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[pdf_file] => patents/07/253/07253507.pdf
[firstpage_image] =>[orig_patent_app_number] => 10975356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/975356 | Semiconductor device | Oct 28, 2004 | Issued |
Array
(
[id] => 447654
[patent_doc_number] => 07253456
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[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Diode structure and integral power switching arrangement'
[patent_app_type] => utility
[patent_app_number] => 10/976436
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[firstpage_image] =>[orig_patent_app_number] => 10976436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/976436 | Diode structure and integral power switching arrangement | Oct 28, 2004 | Issued |
Array
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[id] => 645184
[patent_doc_number] => 07118947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Thin film transistor substrate of a horizontal electric field type LCD and fabricating method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/973886
[patent_app_country] => US
[patent_app_date] => 2004-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 8997
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[pdf_file] => patents/07/118/07118947.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973886
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973886 | Thin film transistor substrate of a horizontal electric field type LCD and fabricating method thereof | Oct 26, 2004 | Issued |
Array
(
[id] => 703083
[patent_doc_number] => 07064389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Semiconductor memory device having full depletive type logic transistors and partial depletion type memory transistors'
[patent_app_type] => utility
[patent_app_number] => 10/969906
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/07/064/07064389.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969906
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969906 | Semiconductor memory device having full depletive type logic transistors and partial depletion type memory transistors | Oct 21, 2004 | Issued |
Array
(
[id] => 6936481
[patent_doc_number] => 20050110042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'POWER SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 10/967166
[patent_app_country] => US
[patent_app_date] => 2004-10-19
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[pdf_file] => publications/A1/0110/20050110042.pdf
[firstpage_image] =>[orig_patent_app_number] => 10967166
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/967166 | Power semiconductor device | Oct 18, 2004 | Issued |
Array
(
[id] => 7008374
[patent_doc_number] => 20050062090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Stack-film trench capacitor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/965160
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[pdf_file] => publications/A1/0062/20050062090.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965160
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965160 | Stack-film trench capacitor and method for manufacturing the same | Oct 14, 2004 | Issued |
Array
(
[id] => 612238
[patent_doc_number] => 07147632
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-12
[patent_title] => 'High-strength microwave antenna assemblies'
[patent_app_type] => utility
[patent_app_number] => 10/961994
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[pdf_file] => patents/07/147/07147632.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961994
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961994 | High-strength microwave antenna assemblies | Oct 6, 2004 | Issued |
Array
(
[id] => 7080665
[patent_doc_number] => 20050046045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Resin-encapsulated package, lead member for the same and method of fabricating the lead member'
[patent_app_type] => utility
[patent_app_number] => 10/957683
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957683 | Resin-encapsulated package, lead member for the same and method of fabricating the lead member | Oct 4, 2004 | Issued |
Array
(
[id] => 677048
[patent_doc_number] => 07087947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/957688
[patent_app_country] => US
[patent_app_date] => 2004-10-05
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[pdf_file] => patents/07/087/07087947.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957688
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957688 | Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same | Oct 4, 2004 | Issued |
Array
(
[id] => 975404
[patent_doc_number] => 06933174
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-08-23
[patent_title] => 'Leadless leadframe package design that provides a greater structural integrity'
[patent_app_type] => utility
[patent_app_number] => 10/956268
[patent_app_country] => US
[patent_app_date] => 2004-09-30
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[pdf_file] => patents/06/933/06933174.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956268
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956268 | Leadless leadframe package design that provides a greater structural integrity | Sep 29, 2004 | Issued |
Array
(
[id] => 535647
[patent_doc_number] => 07180135
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[patent_issue_date] => 2007-02-20
[patent_title] => 'Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load'
[patent_app_type] => utility
[patent_app_number] => 10/951695
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/951695 | Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load | Sep 28, 2004 | Issued |
Array
(
[id] => 5634954
[patent_doc_number] => 20060065927
[patent_country] => US
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[patent_issue_date] => 2006-03-30
[patent_title] => 'Double gate device having a heterojunction source/drain and strained channel'
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[patent_app_number] => 10/952676
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Array
(
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[patent_doc_number] => 20050093058
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[patent_issue_date] => 2005-05-05
[patent_title] => 'Sonos device and methods of manufacturing the same'
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Array
(
[id] => 453982
[patent_doc_number] => 07247922
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[patent_title] => 'Inductor energy loss reduction techniques'
[patent_app_type] => utility
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Array
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[id] => 627370
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[patent_title] => 'Integrated semiconductor device providing for preventing the action of parasitic transistors'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/941586 | Packaging with metal studs formed on solder pads | Sep 13, 2004 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931369 | Integrated circuit device having reduced bow and method for making same | Aug 30, 2004 | Issued |