
Aiqun Li
Examiner (ID: 3811, Phone: (571)270-7736 , Office: P/1768 )
| Most Active Art Unit | 1768 |
| Art Unit(s) | 1796, 1763, 1768, 1766 |
| Total Applications | 951 |
| Issued Applications | 565 |
| Pending Applications | 85 |
| Abandoned Applications | 319 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1113774
[patent_doc_number] => 06803641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'MIM capacitors and methods for fabricating same'
[patent_app_type] => B2
[patent_app_number] => 10/638596
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 35
[patent_no_of_words] => 7739
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803641.pdf
[firstpage_image] =>[orig_patent_app_number] => 10638596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/638596 | MIM capacitors and methods for fabricating same | Aug 10, 2003 | Issued |
Array
(
[id] => 7629386
[patent_doc_number] => 06818970
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Leadless leadframe package design that provides a greater structural integrity'
[patent_app_type] => B1
[patent_app_number] => 10/639226
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 3212
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818970.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639226
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639226 | Leadless leadframe package design that provides a greater structural integrity | Aug 10, 2003 | Issued |
Array
(
[id] => 7611047
[patent_doc_number] => 06841810
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-11
[patent_title] => 'Cell structure for bipolar integrated circuits and method'
[patent_app_type] => utility
[patent_app_number] => 10/637405
[patent_app_country] => US
[patent_app_date] => 2003-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3094
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/841/06841810.pdf
[firstpage_image] =>[orig_patent_app_number] => 10637405
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637405 | Cell structure for bipolar integrated circuits and method | Aug 7, 2003 | Issued |
Array
(
[id] => 729892
[patent_doc_number] => 07042008
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Image sensor and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/636616
[patent_app_country] => US
[patent_app_date] => 2003-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 6160
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/042/07042008.pdf
[firstpage_image] =>[orig_patent_app_number] => 10636616
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/636616 | Image sensor and method of manufacturing the same | Aug 7, 2003 | Issued |
Array
(
[id] => 7120360
[patent_doc_number] => 20050012189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Integrated circuit package with a balanced-part structure'
[patent_app_type] => utility
[patent_app_number] => 10/637045
[patent_app_country] => US
[patent_app_date] => 2003-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6017
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10637045
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637045 | Integrated circuit package with a balanced-part structure | Aug 7, 2003 | Issued |
Array
(
[id] => 1090205
[patent_doc_number] => 06828682
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-07
[patent_title] => 'Substrate voltage connection'
[patent_app_type] => B1
[patent_app_number] => 10/635276
[patent_app_country] => US
[patent_app_date] => 2003-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2733
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/828/06828682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635276
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635276 | Substrate voltage connection | Aug 5, 2003 | Issued |
Array
(
[id] => 7329001
[patent_doc_number] => 20040130012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement'
[patent_app_type] => new
[patent_app_number] => 10/625495
[patent_app_country] => US
[patent_app_date] => 2003-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2328
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20040130012.pdf
[firstpage_image] =>[orig_patent_app_number] => 10625495
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/625495 | Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement | Jul 22, 2003 | Issued |
Array
(
[id] => 7398783
[patent_doc_number] => 20040018676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Semiconductor device having a trench isolation structure and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/623918
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3733
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018676.pdf
[firstpage_image] =>[orig_patent_app_number] => 10623918
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/623918 | Semiconductor device having a trench isolation structure and method for fabricating the same | Jul 20, 2003 | Issued |
Array
(
[id] => 721284
[patent_doc_number] => 07049683
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-23
[patent_title] => 'Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound'
[patent_app_type] => utility
[patent_app_number] => 10/622346
[patent_app_country] => US
[patent_app_date] => 2003-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 46
[patent_no_of_words] => 4967
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/049/07049683.pdf
[firstpage_image] =>[orig_patent_app_number] => 10622346
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622346 | Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound | Jul 18, 2003 | Issued |
Array
(
[id] => 687837
[patent_doc_number] => 07078796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Corrosion-resistant copper bond pad and integrated device'
[patent_app_type] => utility
[patent_app_number] => 10/610745
[patent_app_country] => US
[patent_app_date] => 2003-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 9592
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/078/07078796.pdf
[firstpage_image] =>[orig_patent_app_number] => 10610745
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/610745 | Corrosion-resistant copper bond pad and integrated device | Jun 30, 2003 | Issued |
Array
(
[id] => 706675
[patent_doc_number] => 07065602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Circuit and method for pipelined insertion'
[patent_app_type] => utility
[patent_app_number] => 10/604205
[patent_app_country] => US
[patent_app_date] => 2003-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3107
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/065/07065602.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604205 | Circuit and method for pipelined insertion | Jun 30, 2003 | Issued |
Array
(
[id] => 1037880
[patent_doc_number] => 06873032
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-29
[patent_title] => 'Thermally enhanced chip scale lead on chip semiconductor package and method of making same'
[patent_app_type] => utility
[patent_app_number] => 10/610016
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3212
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/873/06873032.pdf
[firstpage_image] =>[orig_patent_app_number] => 10610016
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/610016 | Thermally enhanced chip scale lead on chip semiconductor package and method of making same | Jun 29, 2003 | Issued |
Array
(
[id] => 476326
[patent_doc_number] => 07227176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Etch stop layer system'
[patent_app_type] => utility
[patent_app_number] => 10/603852
[patent_app_country] => US
[patent_app_date] => 2003-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 9742
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 25
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/227/07227176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10603852
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/603852 | Etch stop layer system | Jun 24, 2003 | Issued |
Array
(
[id] => 783416
[patent_doc_number] => 06992354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'FinFET having suppressed parasitic device characteristics'
[patent_app_type] => utility
[patent_app_number] => 10/604086
[patent_app_country] => US
[patent_app_date] => 2003-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3562
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/992/06992354.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604086
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604086 | FinFET having suppressed parasitic device characteristics | Jun 24, 2003 | Issued |
Array
(
[id] => 7328868
[patent_doc_number] => 20040129973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Power semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/602596
[patent_app_country] => US
[patent_app_date] => 2003-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5920
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20040129973.pdf
[firstpage_image] =>[orig_patent_app_number] => 10602596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/602596 | Power semiconductor device | Jun 24, 2003 | Issued |
Array
(
[id] => 7371637
[patent_doc_number] => 20040079985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/602595
[patent_app_country] => US
[patent_app_date] => 2003-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4720
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20040079985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10602595
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/602595 | Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof | Jun 24, 2003 | Issued |
Array
(
[id] => 7629841
[patent_doc_number] => 06818515
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Method for fabricating semiconductor device with loop line pattern structure'
[patent_app_type] => B1
[patent_app_number] => 10/600466
[patent_app_country] => US
[patent_app_date] => 2003-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 1995
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 8
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818515.pdf
[firstpage_image] =>[orig_patent_app_number] => 10600466
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/600466 | Method for fabricating semiconductor device with loop line pattern structure | Jun 22, 2003 | Issued |
Array
(
[id] => 1068731
[patent_doc_number] => 06844257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens'
[patent_app_type] => utility
[patent_app_number] => 10/601387
[patent_app_country] => US
[patent_app_date] => 2003-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 3737
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/844/06844257.pdf
[firstpage_image] =>[orig_patent_app_number] => 10601387
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/601387 | Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens | Jun 22, 2003 | Issued |
Array
(
[id] => 1068696
[patent_doc_number] => 06844222
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Method for reducing contact impedance of thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/465016
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1929
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/844/06844222.pdf
[firstpage_image] =>[orig_patent_app_number] => 10465016
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/465016 | Method for reducing contact impedance of thin film transistor | Jun 17, 2003 | Issued |
Array
(
[id] => 7615041
[patent_doc_number] => 06897485
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-24
[patent_title] => 'Device for optical and/or electrical data transmission and/or processing'
[patent_app_type] => utility
[patent_app_number] => 10/462956
[patent_app_country] => US
[patent_app_date] => 2003-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4087
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/897/06897485.pdf
[firstpage_image] =>[orig_patent_app_number] => 10462956
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/462956 | Device for optical and/or electrical data transmission and/or processing | Jun 16, 2003 | Issued |