
Aiqun Li
Examiner (ID: 3811, Phone: (571)270-7736 , Office: P/1768 )
| Most Active Art Unit | 1768 |
| Art Unit(s) | 1796, 1763, 1768, 1766 |
| Total Applications | 951 |
| Issued Applications | 565 |
| Pending Applications | 85 |
| Abandoned Applications | 319 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1237296
[patent_doc_number] => 06690091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-10
[patent_title] => 'Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer'
[patent_app_type] => B1
[patent_app_number] => 09/666316
[patent_app_country] => US
[patent_app_date] => 2000-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3648
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/690/06690091.pdf
[firstpage_image] =>[orig_patent_app_number] => 09666316
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/666316 | Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer | Sep 20, 2000 | Issued |
Array
(
[id] => 1352633
[patent_doc_number] => 06583515
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Ball grid array package for enhanced stress tolerance'
[patent_app_type] => B1
[patent_app_number] => 09/654540
[patent_app_country] => US
[patent_app_date] => 2000-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3617
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583515.pdf
[firstpage_image] =>[orig_patent_app_number] => 09654540
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654540 | Ball grid array package for enhanced stress tolerance | Aug 31, 2000 | Issued |
Array
(
[id] => 1056976
[patent_doc_number] => 06856021
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-15
[patent_title] => 'Semiconductor device having aluminum alloy conductors'
[patent_app_type] => utility
[patent_app_number] => 09/648455
[patent_app_country] => US
[patent_app_date] => 2000-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3881
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/856/06856021.pdf
[firstpage_image] =>[orig_patent_app_number] => 09648455
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/648455 | Semiconductor device having aluminum alloy conductors | Aug 27, 2000 | Issued |
Array
(
[id] => 1360992
[patent_doc_number] => 06577018
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Integrated circuit device having reduced bow and method for making same'
[patent_app_type] => B1
[patent_app_number] => 09/648316
[patent_app_country] => US
[patent_app_date] => 2000-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3969
[patent_no_of_claims] => 33
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/577/06577018.pdf
[firstpage_image] =>[orig_patent_app_number] => 09648316
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/648316 | Integrated circuit device having reduced bow and method for making same | Aug 24, 2000 | Issued |
Array
(
[id] => 530194
[patent_doc_number] => 07179661
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-20
[patent_title] => 'Chemical mechanical polishing test structures and methods for inspecting the same'
[patent_app_type] => utility
[patent_app_number] => 09/648095
[patent_app_country] => US
[patent_app_date] => 2000-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 52
[patent_no_of_words] => 23359
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/179/07179661.pdf
[firstpage_image] =>[orig_patent_app_number] => 09648095
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/648095 | Chemical mechanical polishing test structures and methods for inspecting the same | Aug 24, 2000 | Issued |
Array
(
[id] => 1207029
[patent_doc_number] => 06717209
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Semiconductor device having junction diode and fabricating method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/645285
[patent_app_country] => US
[patent_app_date] => 2000-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 5572
[patent_no_of_claims] => 17
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717209.pdf
[firstpage_image] =>[orig_patent_app_number] => 09645285
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/645285 | Semiconductor device having junction diode and fabricating method therefor | Aug 23, 2000 | Issued |
| 09/645654 | Polymer redistribution of flip chip bond pads | Aug 23, 2000 | Abandoned |
Array
(
[id] => 1419550
[patent_doc_number] => 06525409
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'CCD mold package with improved heat radiation structure'
[patent_app_type] => B1
[patent_app_number] => 09/644695
[patent_app_country] => US
[patent_app_date] => 2000-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3537
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525409.pdf
[firstpage_image] =>[orig_patent_app_number] => 09644695
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644695 | CCD mold package with improved heat radiation structure | Aug 23, 2000 | Issued |
Array
(
[id] => 1196700
[patent_doc_number] => 06727169
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'Method of making conformal lining layers for damascene metallization'
[patent_app_type] => B1
[patent_app_number] => 09/644416
[patent_app_country] => US
[patent_app_date] => 2000-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 10581
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/727/06727169.pdf
[firstpage_image] =>[orig_patent_app_number] => 09644416
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644416 | Method of making conformal lining layers for damascene metallization | Aug 22, 2000 | Issued |
Array
(
[id] => 1264316
[patent_doc_number] => 06660565
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Flip chip molded/exposed die process and package structure'
[patent_app_type] => B1
[patent_app_number] => 09/640534
[patent_app_country] => US
[patent_app_date] => 2000-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3165
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/660/06660565.pdf
[firstpage_image] =>[orig_patent_app_number] => 09640534
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/640534 | Flip chip molded/exposed die process and package structure | Aug 16, 2000 | Issued |
Array
(
[id] => 1065611
[patent_doc_number] => 06846737
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-25
[patent_title] => 'Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 09/639625
[patent_app_country] => US
[patent_app_date] => 2000-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3385
[patent_no_of_claims] => 36
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/846/06846737.pdf
[firstpage_image] =>[orig_patent_app_number] => 09639625
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/639625 | Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials | Aug 14, 2000 | Issued |
Array
(
[id] => 7634378
[patent_doc_number] => 06657242
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Trench-isolated bipolar devices'
[patent_app_type] => B1
[patent_app_number] => 09/632936
[patent_app_country] => US
[patent_app_date] => 2000-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 10500
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/657/06657242.pdf
[firstpage_image] =>[orig_patent_app_number] => 09632936
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/632936 | Trench-isolated bipolar devices | Aug 3, 2000 | Issued |
Array
(
[id] => 1380549
[patent_doc_number] => 06563216
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Semiconductor device having a bump electrode'
[patent_app_type] => B1
[patent_app_number] => 09/632324
[patent_app_country] => US
[patent_app_date] => 2000-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/563/06563216.pdf
[firstpage_image] =>[orig_patent_app_number] => 09632324
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/632324 | Semiconductor device having a bump electrode | Aug 3, 2000 | Issued |
Array
(
[id] => 1246736
[patent_doc_number] => 06677682
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-13
[patent_title] => 'Multilayer interconnection structure including an alignment mark'
[patent_app_type] => B1
[patent_app_number] => 09/620555
[patent_app_country] => US
[patent_app_date] => 2000-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/677/06677682.pdf
[firstpage_image] =>[orig_patent_app_number] => 09620555
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/620555 | Multilayer interconnection structure including an alignment mark | Jul 19, 2000 | Issued |
Array
(
[id] => 1056769
[patent_doc_number] => 06855954
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-15
[patent_title] => 'Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 09/619556
[patent_app_country] => US
[patent_app_date] => 2000-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_no_of_words] => 10931
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/855/06855954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09619556
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/619556 | Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor | Jul 18, 2000 | Issued |
Array
(
[id] => 1266545
[patent_doc_number] => 06661082
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Flip chip substrate design'
[patent_app_type] => B1
[patent_app_number] => 09/619115
[patent_app_country] => US
[patent_app_date] => 2000-07-19
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/661/06661082.pdf
[firstpage_image] =>[orig_patent_app_number] => 09619115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/619115 | Flip chip substrate design | Jul 18, 2000 | Issued |
Array
(
[id] => 1120935
[patent_doc_number] => 06798064
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-28
[patent_title] => 'Electronic component and method of manufacture'
[patent_app_type] => B1
[patent_app_number] => 09/614794
[patent_app_country] => US
[patent_app_date] => 2000-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/798/06798064.pdf
[firstpage_image] =>[orig_patent_app_number] => 09614794
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/614794 | Electronic component and method of manufacture | Jul 11, 2000 | Issued |
Array
(
[id] => 1221715
[patent_doc_number] => 06703666
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-09
[patent_title] => 'Thin film resistor device and a method of manufacture therefor'
[patent_app_type] => B1
[patent_app_number] => 09/614992
[patent_app_country] => US
[patent_app_date] => 2000-07-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/703/06703666.pdf
[firstpage_image] =>[orig_patent_app_number] => 09614992
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/614992 | Thin film resistor device and a method of manufacture therefor | Jul 11, 2000 | Issued |
| 09/604534 | Interconnection for accommadating thermal expansion for low elastic modulus dielectrics | Jun 26, 2000 | Abandoned |
Array
(
[id] => 1509347
[patent_doc_number] => 06441440
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Semiconductor device and circuit having low tolerance to ionizing radiation'
[patent_app_type] => B1
[patent_app_number] => 09/590806
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/441/06441440.pdf
[firstpage_image] =>[orig_patent_app_number] => 09590806
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590806 | Semiconductor device and circuit having low tolerance to ionizing radiation | Jun 8, 2000 | Issued |