
Ajay Arora
Examiner (ID: 12666, Phone: (571)272-8347 , Office: P/2892 )
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2892, 2811 |
| Total Applications | 1272 |
| Issued Applications | 1029 |
| Pending Applications | 83 |
| Abandoned Applications | 184 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19712671
[patent_doc_number] => 20250022813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => MULTIDIE SUPPORTS AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 18/902442
[patent_app_country] => US
[patent_app_date] => 2024-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8357
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18902442
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/902442 | MULTIDIE SUPPORTS AND RELATED METHODS | Sep 29, 2024 | Pending |
Array
(
[id] => 19589750
[patent_doc_number] => 20240387307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => SEMICONDUCTOR PACKAGE WITH STIFFENER STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/789496
[patent_app_country] => US
[patent_app_date] => 2024-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789496
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/789496 | Semiconductor package with stiffener structure and method of manufacturing the same | Jul 29, 2024 | Issued |
Array
(
[id] => 20540618
[patent_doc_number] => 12557708
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-17
[patent_title] => Power module with improved conductive paths
[patent_app_type] => utility
[patent_app_number] => 18/770232
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 39
[patent_no_of_words] => 47939
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 650
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770232
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/770232 | Power module with improved conductive paths | Jul 10, 2024 | Issued |
Array
(
[id] => 20132237
[patent_doc_number] => 12374555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Die sidewall coatings and related methods
[patent_app_type] => utility
[patent_app_number] => 18/742204
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 122
[patent_no_of_words] => 29141
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/742204 | Die sidewall coatings and related methods | Jun 12, 2024 | Issued |
Array
(
[id] => 19751596
[patent_doc_number] => 20250040161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/673261
[patent_app_country] => US
[patent_app_date] => 2024-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12101
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673261
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/673261 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD | May 22, 2024 | Pending |
Array
(
[id] => 19392809
[patent_doc_number] => 20240282679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => METHODS OF FORMING PACKAGED SEMICONDUCTOR DEVICES AND LEADFRAMES FOR SEMICONDUCTOR DEVICE PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/654125
[patent_app_country] => US
[patent_app_date] => 2024-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654125
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/654125 | Packaged semiconductor devices with leadframes having tie bar with recessed cavity | May 2, 2024 | Issued |
Array
(
[id] => 20113393
[patent_doc_number] => 12364150
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Display apparatus with penetrating portion and method of manufacturing same
[patent_app_type] => utility
[patent_app_number] => 18/637063
[patent_app_country] => US
[patent_app_date] => 2024-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 1018
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637063
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/637063 | Display apparatus with penetrating portion and method of manufacturing same | Apr 15, 2024 | Issued |
Array
(
[id] => 20118367
[patent_doc_number] => 12368085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Integration of semiconductor device assemblies with thermal dissipation mechanisms
[patent_app_type] => utility
[patent_app_number] => 18/635186
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 39
[patent_no_of_words] => 2728
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635186
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/635186 | Integration of semiconductor device assemblies with thermal dissipation mechanisms | Apr 14, 2024 | Issued |
Array
(
[id] => 19335572
[patent_doc_number] => 20240250002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/623992
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16726
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623992
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623992 | Semiconductor device including through die via | Mar 31, 2024 | Issued |
Array
(
[id] => 19452814
[patent_doc_number] => 20240312944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => Semiconductor Die and Method for Attaching a Semiconductor Die to a Solid Structure with Controlled Fillet Height
[patent_app_type] => utility
[patent_app_number] => 18/604807
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4245
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604807
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604807 | Semiconductor Die and Method for Attaching a Semiconductor Die to a Solid Structure with Controlled Fillet Height | Mar 13, 2024 | Pending |
Array
(
[id] => 19484385
[patent_doc_number] => 20240332427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/604840
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12480
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604840
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604840 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Mar 13, 2024 | Pending |
Array
(
[id] => 19648443
[patent_doc_number] => 20240422963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/604584
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7880
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604584
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604584 | SEMICONDUCTOR MEMORY DEVICE | Mar 13, 2024 | Pending |
Array
(
[id] => 20900751
[patent_doc_number] => 12708034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-11
[patent_title] => Sensor packages
[patent_app_type] => utility
[patent_app_number] => 18/592090
[patent_app_country] => US
[patent_app_date] => 2024-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 48
[patent_no_of_words] => 0
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592090
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/592090 | SENSOR PACKAGES | Feb 28, 2024 | Pending |
Array
(
[id] => 20196836
[patent_doc_number] => 20250273546
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => INTEGRATED CIRCUIT PACKAGING WITH INSULATION STRUCTURE TO CONTROL GAP HEIGHT AND DIE TILT
[patent_app_type] => utility
[patent_app_number] => 18/583987
[patent_app_country] => US
[patent_app_date] => 2024-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2307
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583987
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583987 | Integrated circuit packaging with insulation structure to control gap height and die tilt | Feb 21, 2024 | Issued |
Array
(
[id] => 19712856
[patent_doc_number] => 20250022998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => FILM PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/583947
[patent_app_country] => US
[patent_app_date] => 2024-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583947
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583947 | FILM PACKAGE | Feb 21, 2024 | Pending |
Array
(
[id] => 19407139
[patent_doc_number] => 20240290650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => STAGE APPARATUS, LITHOGRAPHY APPARATUS, AND ARTICLE MANUFACTURING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/584481
[patent_app_country] => US
[patent_app_date] => 2024-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584481
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/584481 | STAGE APPARATUS, LITHOGRAPHY APPARATUS, AND ARTICLE MANUFACTURING METHOD | Feb 21, 2024 | Pending |
Array
(
[id] => 19420920
[patent_doc_number] => 20240297044
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => PROCESS FOR MANUFACTURING LOCALIZED ION IMPLANTS IN SILICON-CARBIDE POWER ELECTRONIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/583752
[patent_app_country] => US
[patent_app_date] => 2024-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5757
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583752
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583752 | PROCESS FOR MANUFACTURING LOCALIZED ION IMPLANTS IN SILICON-CARBIDE POWER ELECTRONIC DEVICES | Feb 20, 2024 | Pending |
Array
(
[id] => 19384828
[patent_doc_number] => 20240274698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/583764
[patent_app_country] => US
[patent_app_date] => 2024-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16185
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -33
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583764
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Feb 20, 2024 | Pending |
Array
(
[id] => 20916913
[patent_doc_number] => 12713782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-18
[patent_title] => Display device with electrode-barrier structure and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/583738
[patent_app_country] => US
[patent_app_date] => 2024-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583738
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583738 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE | Feb 20, 2024 | Pending |
Array
(
[id] => 20734854
[patent_doc_number] => 12642122
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-26
[patent_title] => Electronic devices with a redistribution layer and methods of manufacturing electronic devices with a redistribution layer
[patent_app_type] => utility
[patent_app_number] => 18/444951
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 39
[patent_no_of_words] => 5117
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444951
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444951 | Electronic devices with a redistribution layer and methods of manufacturing electronic devices with a redistribution layer | Feb 18, 2024 | Issued |