Search

Ajay Arora

Examiner (ID: 12666, Phone: (571)272-8347 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892, 2811
Total Applications
1272
Issued Applications
1029
Pending Applications
83
Abandoned Applications
184

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17863441 [patent_doc_number] => 11444606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Spike pulse generation circuit comprising single silicon device [patent_app_type] => utility [patent_app_number] => 17/168395 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9492 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168395
Spike pulse generation circuit comprising single silicon device Feb 4, 2021 Issued
Array ( [id] => 17623215 [patent_doc_number] => 11342279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Semiconductor device and amplifier having bonding wire and conductive member [patent_app_type] => utility [patent_app_number] => 17/167213 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167213
Semiconductor device and amplifier having bonding wire and conductive member Feb 3, 2021 Issued
Array ( [id] => 17010950 [patent_doc_number] => 20210242111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => POWER SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/160612 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160612
Power semiconductor device and method for fabricating a power semiconductor device Jan 27, 2021 Issued
Array ( [id] => 16850664 [patent_doc_number] => 20210151409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => STAGGERED DIE STACKING ACROSS HETEROGENEOUS MODULES [patent_app_type] => utility [patent_app_number] => 17/158385 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158385
Staggered die stacking across heterogeneous modules Jan 25, 2021 Issued
Array ( [id] => 16812290 [patent_doc_number] => 20210134845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/147189 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147189
Display device with metal layer having pinhole Jan 11, 2021 Issued
Array ( [id] => 18623802 [patent_doc_number] => 11756858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Power module with housing having bending sections [patent_app_type] => utility [patent_app_number] => 17/140145 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4402 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140145
Power module with housing having bending sections Jan 3, 2021 Issued
Array ( [id] => 19296207 [patent_doc_number] => 12035586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Display panel comprising a post spacer, manufacturing method and display device [patent_app_type] => utility [patent_app_number] => 17/312905 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4450 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17312905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/312905
Display panel comprising a post spacer, manufacturing method and display device Dec 29, 2020 Issued
Array ( [id] => 18190594 [patent_doc_number] => 11581195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor package having wettable lead flank and method of making the same [patent_app_type] => utility [patent_app_number] => 17/129319 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3641 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129319
Semiconductor package having wettable lead flank and method of making the same Dec 20, 2020 Issued
Array ( [id] => 17025460 [patent_doc_number] => 20210249332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => INTEGRATION OF SEMICONDUCTOR DEVICE ASSEMBLIES WITH THERMAL DISSIPATION MECHANISMS [patent_app_type] => utility [patent_app_number] => 17/247585 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247585
Integration of semiconductor device assemblies with thermal dissipation mechanisms Dec 16, 2020 Issued
Array ( [id] => 17676767 [patent_doc_number] => 20220189934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => Backside Interconnection Interface Die For Integrated Circuits Package [patent_app_type] => utility [patent_app_number] => 17/121868 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121868
Backside interconnection interface die for integrated circuits package Dec 14, 2020 Issued
Array ( [id] => 17676672 [patent_doc_number] => 20220189839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING [patent_app_type] => utility [patent_app_number] => 17/122167 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122167
INTER-COMPONENT MATERIAL IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING Dec 14, 2020 Abandoned
Array ( [id] => 17676690 [patent_doc_number] => 20220189857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SUSPENDED SEMICONDUCTOR DIES [patent_app_type] => utility [patent_app_number] => 17/120941 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120941
Suspended semiconductor dies Dec 13, 2020 Issued
Array ( [id] => 16731327 [patent_doc_number] => 20210098475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/117628 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117628
Integrated circuit with different memory gate work functions Dec 9, 2020 Issued
Array ( [id] => 16904805 [patent_doc_number] => 20210183721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/109157 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109157
Semiconductor device with heating structure Dec 1, 2020 Issued
Array ( [id] => 17787786 [patent_doc_number] => 11410922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Semiconductor device comprising a capacitor [patent_app_type] => utility [patent_app_number] => 17/107552 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107552
Semiconductor device comprising a capacitor Nov 29, 2020 Issued
Array ( [id] => 16715679 [patent_doc_number] => 20210082826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DIE MOUNT [patent_app_type] => utility [patent_app_number] => 17/102726 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102726
Semiconductor package having wafer-level active die and external die mount Nov 23, 2020 Issued
Array ( [id] => 16715864 [patent_doc_number] => 20210083011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/103076 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103076
Organic light-emitting display apparatus comprising quantum dots Nov 23, 2020 Issued
Array ( [id] => 17630647 [patent_doc_number] => 20220165662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR DEVICE WITH AIR GAPS BETWEEN ADJACENT CONDUCTIVE LINES [patent_app_type] => utility [patent_app_number] => 17/101281 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101281
Semiconductor device with air gaps between adjacent conductive lines Nov 22, 2020 Issued
Array ( [id] => 17630661 [patent_doc_number] => 20220165676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHOD AND RELATED STRUCTURE TO AUTHENTICATE INTEGRATED CIRCUIT WITH AUTHENTICATION FILM [patent_app_type] => utility [patent_app_number] => 16/953441 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953441
Method and related structure to authenticate integrated circuit with authentication film Nov 19, 2020 Issued
Array ( [id] => 18097397 [patent_doc_number] => 20220415738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Power Semiconductor Device and Method of Manufacturing the Same, and Power Conversion Device [patent_app_type] => utility [patent_app_number] => 17/771206 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/771206
Power semiconductor device and method of manufacturing the same, and power conversion device Nov 17, 2020 Issued
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