Search

Ajay Arora

Examiner (ID: 12666, Phone: (571)272-8347 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892, 2811
Total Applications
1272
Issued Applications
1029
Pending Applications
83
Abandoned Applications
184

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18578964 [patent_doc_number] => 11735504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Power module package baseplate with step recess design [patent_app_type] => utility [patent_app_number] => 16/949869 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949869
Power module package baseplate with step recess design Nov 17, 2020 Issued
Array ( [id] => 17439059 [patent_doc_number] => 11264400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Nitride-free spacer or oxide spacer for embedded flash memory [patent_app_type] => utility [patent_app_number] => 16/950144 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950144 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950144
Nitride-free spacer or oxide spacer for embedded flash memory Nov 16, 2020 Issued
Array ( [id] => 18088613 [patent_doc_number] => 11538752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Contact area structure with organic adhesive layer between inorganic conductive layer and transparent conductive layer [patent_app_type] => utility [patent_app_number] => 17/094631 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3494 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094631
Contact area structure with organic adhesive layer between inorganic conductive layer and transparent conductive layer Nov 9, 2020 Issued
Array ( [id] => 16631613 [patent_doc_number] => 20210050266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => TUNNEL MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND BUILT-IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/089194 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089194
Tunnel magnetoresistive effect element, magnetic memory, and built-in memory Nov 3, 2020 Issued
Array ( [id] => 17745616 [patent_doc_number] => 11393697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Semiconductor chip gettering [patent_app_type] => utility [patent_app_number] => 17/087388 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087388
Semiconductor chip gettering Nov 1, 2020 Issued
Array ( [id] => 19063180 [patent_doc_number] => 11942432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Method for packaging COF [patent_app_type] => utility [patent_app_number] => 17/615797 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2891 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17615797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/615797
Method for packaging COF Oct 12, 2020 Issued
Array ( [id] => 17941729 [patent_doc_number] => 11476188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Fabrication of embedded die packaging comprising laser drilled vias [patent_app_type] => utility [patent_app_number] => 17/065886 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 38 [patent_no_of_words] => 6926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065886
Fabrication of embedded die packaging comprising laser drilled vias Oct 7, 2020 Issued
Array ( [id] => 20132280 [patent_doc_number] => 12374598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Semiconductor apparatus including Peltier element [patent_app_type] => utility [patent_app_number] => 17/757087 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 52 [patent_no_of_words] => 10620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/757087
Semiconductor apparatus including Peltier element Oct 7, 2020 Issued
Array ( [id] => 16617390 [patent_doc_number] => 20210036043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => CONCAVE REFLECTOR FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR (CIS) [patent_app_type] => utility [patent_app_number] => 17/063801 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063801
Concave reflector for complementary metal oxide semiconductor image sensor (CIS) Oct 5, 2020 Issued
Array ( [id] => 18009344 [patent_doc_number] => 20220368111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Polarised Emission from Quantum Wires in Cubic GaN [patent_app_type] => utility [patent_app_number] => 17/765751 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765751
Polarised emission from quantum wires in cubic GaN Sep 29, 2020 Issued
Array ( [id] => 16586237 [patent_doc_number] => 20210020639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR ARRANGEMENT HAVING CONTINUOUS SPACERS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/039755 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039755
Semiconductor arrangement having continuous spacers and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 16586238 [patent_doc_number] => 20210020640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR ARRANGEMENT HAVING CONTINUOUS SPACERS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/039770 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039770
Semiconductor arrangement having continuous spacers and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 17590731 [patent_doc_number] => 11329008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Method for manufacturing semiconductor package for warpage control [patent_app_type] => utility [patent_app_number] => 17/028862 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028862
Method for manufacturing semiconductor package for warpage control Sep 21, 2020 Issued
Array ( [id] => 16624934 [patent_doc_number] => 20210043587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SECURITY CHIP, SECURITY CHIP PRODUCTION METHOD AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/026213 [patent_app_country] => US [patent_app_date] => 2020-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026213
Security chip, security chip production method and electronic device Sep 18, 2020 Issued
Array ( [id] => 17085473 [patent_doc_number] => 20210280480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/010926 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010926
Semiconductor device having a resin layer sealing a plurality of semiconductor chips stacked on first semiconductor chips Sep 2, 2020 Issued
Array ( [id] => 17448234 [patent_doc_number] => 20220068739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => ELECTRIONIC DEVICES WITH INTERPOSER AND REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 17/008239 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008239
Electrionic devices with interposer and redistribution layer Aug 30, 2020 Issued
Array ( [id] => 16731226 [patent_doc_number] => 20210098374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => TERMINAL AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/003124 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003124
Terminal configuration and semiconductor device Aug 25, 2020 Issued
Array ( [id] => 16487902 [patent_doc_number] => 20200381511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Semiconductor Device with Drain Structure and Metal Drain Electrode [patent_app_type] => utility [patent_app_number] => 16/998152 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998152
Semiconductor device with drain structure and metal drain electrode Aug 19, 2020 Issued
Array ( [id] => 18999141 [patent_doc_number] => 11915997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Thermal management of GPU-HBM package by microchannel integrated substrate [patent_app_type] => utility [patent_app_number] => 16/990943 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4342 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990943
Thermal management of GPU-HBM package by microchannel integrated substrate Aug 10, 2020 Issued
Array ( [id] => 19376709 [patent_doc_number] => 12068289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Power module [patent_app_type] => utility [patent_app_number] => 17/596558 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 39 [patent_no_of_words] => 54098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17596558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/596558
Power module Aug 5, 2020 Issued
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