Search

Ajay Arora

Examiner (ID: 4150, Phone: (571)272-8347 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2892, 2811
Total Applications
1236
Issued Applications
1005
Pending Applications
90
Abandoned Applications
181

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20132280 [patent_doc_number] => 12374598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Semiconductor apparatus including Peltier element [patent_app_type] => utility [patent_app_number] => 17/757087 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 52 [patent_no_of_words] => 10620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/757087
Semiconductor apparatus including Peltier element Oct 7, 2020 Issued
Array ( [id] => 17941729 [patent_doc_number] => 11476188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Fabrication of embedded die packaging comprising laser drilled vias [patent_app_type] => utility [patent_app_number] => 17/065886 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 38 [patent_no_of_words] => 6926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065886
Fabrication of embedded die packaging comprising laser drilled vias Oct 7, 2020 Issued
Array ( [id] => 16617390 [patent_doc_number] => 20210036043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => CONCAVE REFLECTOR FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR (CIS) [patent_app_type] => utility [patent_app_number] => 17/063801 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063801
Concave reflector for complementary metal oxide semiconductor image sensor (CIS) Oct 5, 2020 Issued
Array ( [id] => 18009344 [patent_doc_number] => 20220368111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Polarised Emission from Quantum Wires in Cubic GaN [patent_app_type] => utility [patent_app_number] => 17/765751 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765751
Polarised emission from quantum wires in cubic GaN Sep 29, 2020 Issued
Array ( [id] => 16586237 [patent_doc_number] => 20210020639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR ARRANGEMENT HAVING CONTINUOUS SPACERS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/039755 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039755
Semiconductor arrangement having continuous spacers and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 16586238 [patent_doc_number] => 20210020640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR ARRANGEMENT HAVING CONTINUOUS SPACERS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/039770 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039770
Semiconductor arrangement having continuous spacers and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 17590731 [patent_doc_number] => 11329008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Method for manufacturing semiconductor package for warpage control [patent_app_type] => utility [patent_app_number] => 17/028862 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028862
Method for manufacturing semiconductor package for warpage control Sep 21, 2020 Issued
Array ( [id] => 16624934 [patent_doc_number] => 20210043587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SECURITY CHIP, SECURITY CHIP PRODUCTION METHOD AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/026213 [patent_app_country] => US [patent_app_date] => 2020-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026213
Security chip, security chip production method and electronic device Sep 18, 2020 Issued
Array ( [id] => 17085473 [patent_doc_number] => 20210280480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/010926 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010926
Semiconductor device having a resin layer sealing a plurality of semiconductor chips stacked on first semiconductor chips Sep 2, 2020 Issued
Array ( [id] => 17448234 [patent_doc_number] => 20220068739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => ELECTRIONIC DEVICES WITH INTERPOSER AND REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 17/008239 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008239
Electrionic devices with interposer and redistribution layer Aug 30, 2020 Issued
Array ( [id] => 16731226 [patent_doc_number] => 20210098374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => TERMINAL AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/003124 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003124
Terminal configuration and semiconductor device Aug 25, 2020 Issued
Array ( [id] => 16487902 [patent_doc_number] => 20200381511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Semiconductor Device with Drain Structure and Metal Drain Electrode [patent_app_type] => utility [patent_app_number] => 16/998152 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998152
Semiconductor device with drain structure and metal drain electrode Aug 19, 2020 Issued
Array ( [id] => 18999141 [patent_doc_number] => 11915997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Thermal management of GPU-HBM package by microchannel integrated substrate [patent_app_type] => utility [patent_app_number] => 16/990943 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4342 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990943
Thermal management of GPU-HBM package by microchannel integrated substrate Aug 10, 2020 Issued
Array ( [id] => 16951760 [patent_doc_number] => 20210210452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => INTEGRATED PASSIVE DEVICE (IPD) COUPLED TO FRONT SIDE OF INTEGRATED DEVICE [patent_app_type] => utility [patent_app_number] => 16/987122 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/987122
INTEGRATED PASSIVE DEVICE (IPD) COUPLED TO FRONT SIDE OF INTEGRATED DEVICE Aug 5, 2020 Abandoned
Array ( [id] => 19376709 [patent_doc_number] => 12068289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Power module [patent_app_type] => utility [patent_app_number] => 17/596558 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 39 [patent_no_of_words] => 54098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17596558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/596558
Power module Aug 5, 2020 Issued
Array ( [id] => 16455982 [patent_doc_number] => 20200365408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR PACKAGES WITH DIE INCLUDING CAVITIES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/985995 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16985995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/985995
Semiconductor packages with die including cavities and related methods Aug 4, 2020 Issued
Array ( [id] => 16609404 [patent_doc_number] => 10910420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor switching device separate by device isolation [patent_app_type] => utility [patent_app_number] => 16/983767 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983767 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983767
Semiconductor switching device separate by device isolation Aug 2, 2020 Issued
Array ( [id] => 16896530 [patent_doc_number] => 11038093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Wirebond cross-talk reduction for quantum computing chips [patent_app_type] => utility [patent_app_number] => 16/943572 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4655 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943572
Wirebond cross-talk reduction for quantum computing chips Jul 29, 2020 Issued
Array ( [id] => 19487304 [patent_doc_number] => 12107029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Power module with graphite plate [patent_app_type] => utility [patent_app_number] => 17/595230 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 45 [patent_no_of_words] => 50179 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/595230
Power module with graphite plate Jul 28, 2020 Issued
Array ( [id] => 17093024 [patent_doc_number] => 11121222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Semiconductor devices with graded dopant regions [patent_app_type] => utility [patent_app_number] => 16/947294 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1882 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947294
Semiconductor devices with graded dopant regions Jul 26, 2020 Issued
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