
Ajay Arora
Examiner (ID: 12666, Phone: (571)272-8347 , Office: P/2892 )
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2892, 2811 |
| Total Applications | 1272 |
| Issued Applications | 1029 |
| Pending Applications | 83 |
| Abandoned Applications | 184 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10570323
[patent_doc_number] => 09293502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-22
[patent_title] => 'Semiconductor switching device separated by device isolation'
[patent_app_type] => utility
[patent_app_number] => 13/951626
[patent_app_country] => US
[patent_app_date] => 2013-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3514
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951626
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951626 | Semiconductor switching device separated by device isolation | Jul 25, 2013 | Issued |
Array
(
[id] => 10597317
[patent_doc_number] => 09318412
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'Method for semiconductor self-aligned patterning'
[patent_app_type] => utility
[patent_app_number] => 13/951717
[patent_app_country] => US
[patent_app_date] => 2013-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3256
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951717
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951717 | Method for semiconductor self-aligned patterning | Jul 25, 2013 | Issued |
Array
(
[id] => 10125301
[patent_doc_number] => 09159667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure'
[patent_app_type] => utility
[patent_app_number] => 13/951654
[patent_app_country] => US
[patent_app_date] => 2013-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5907
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951654
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951654 | Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure | Jul 25, 2013 | Issued |
Array
(
[id] => 9277885
[patent_doc_number] => 20140027853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'Fluctuation Resistant Low Access Resistance Fully Depleted SOI Transistor with Improved Channel Thickness Control and Reduced Access Resistance'
[patent_app_type] => utility
[patent_app_number] => 13/950810
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5094
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950810
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950810 | Fluctuation resistant low access resistance fully depleted SOI transistor with improved channel thickness control and reduced access resistance | Jul 24, 2013 | Issued |
Array
(
[id] => 10544668
[patent_doc_number] => 09269804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-23
[patent_title] => 'Gate recessed FDSOI transistor with sandwich of active and etch control layers'
[patent_app_type] => utility
[patent_app_number] => 13/950868
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 4237
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950868
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950868 | Gate recessed FDSOI transistor with sandwich of active and etch control layers | Jul 24, 2013 | Issued |
Array
(
[id] => 9277840
[patent_doc_number] => 20140027808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'LATERAL CARRIER INJECTION INFRARED LIGHT EMITTING DIODE STRUCTURE, METHOD AND APPLICATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/950709
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4919
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950709
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950709 | LATERAL CARRIER INJECTION INFRARED LIGHT EMITTING DIODE STRUCTURE, METHOD AND APPLICATIONS | Jul 24, 2013 | Abandoned |
Array
(
[id] => 9996459
[patent_doc_number] => 09041061
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-26
[patent_title] => 'III-V device with overlapped extension regions using replacement gate'
[patent_app_type] => utility
[patent_app_number] => 13/950788
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5639
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950788
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950788 | III-V device with overlapped extension regions using replacement gate | Jul 24, 2013 | Issued |
Array
(
[id] => 9303756
[patent_doc_number] => 20140042430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/951338
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 23345
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951338
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951338 | Thin film transistor substrate with pixel matrix | Jul 24, 2013 | Issued |
Array
(
[id] => 9996458
[patent_doc_number] => 09041060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-26
[patent_title] => 'III-V FET device with overlapped extension regions using gate last'
[patent_app_type] => utility
[patent_app_number] => 13/950758
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5189
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950758
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950758 | III-V FET device with overlapped extension regions using gate last | Jul 24, 2013 | Issued |
Array
(
[id] => 9488300
[patent_doc_number] => 20140138706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-22
[patent_title] => 'ELECTRONIC CIRCUIT, PRODUCTION METHOD THEREOF, AND ELECTRONIC COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 13/951324
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4568
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951324
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951324 | Electronic circuit, production method thereof, and electronic component | Jul 24, 2013 | Issued |
Array
(
[id] => 11187794
[patent_doc_number] => 09419206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-16
[patent_title] => 'Magnetic sensor and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 13/951093
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 37
[patent_no_of_words] => 6758
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951093
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/951093 | Magnetic sensor and method of fabricating the same | Jul 24, 2013 | Issued |
Array
(
[id] => 9277886
[patent_doc_number] => 20140027854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'Fluctuation Resistant FDSOI Transistor with Implanted Subchannel'
[patent_app_type] => utility
[patent_app_number] => 13/950834
[patent_app_country] => US
[patent_app_date] => 2013-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5136
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950834
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950834 | Fluctuation resistant FDSOI transistor with implanted subchannel | Jul 24, 2013 | Issued |
Array
(
[id] => 9413420
[patent_doc_number] => 08697456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-15
[patent_title] => 'Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon'
[patent_app_type] => utility
[patent_app_number] => 13/932288
[patent_app_country] => US
[patent_app_date] => 2013-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 3701
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932288
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/932288 | Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon | Jun 30, 2013 | Issued |
Array
(
[id] => 9888876
[patent_doc_number] => 08975130
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-10
[patent_title] => 'Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices'
[patent_app_type] => utility
[patent_app_number] => 13/930611
[patent_app_country] => US
[patent_app_date] => 2013-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 5955
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930611
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/930611 | Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices | Jun 27, 2013 | Issued |
Array
(
[id] => 10950573
[patent_doc_number] => 20140353594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-04
[patent_title] => 'OLED Panel, Manufacturing Method, and Related Testing Method'
[patent_app_type] => utility
[patent_app_number] => 13/985910
[patent_app_country] => US
[patent_app_date] => 2013-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5040
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985910
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/985910 | OLED Panel, Manufacturing Method, and Related Testing Method | Jun 27, 2013 | Abandoned |
Array
(
[id] => 9875128
[patent_doc_number] => 08962395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'QFN package and manufacturing process thereof'
[patent_app_type] => utility
[patent_app_number] => 13/918518
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 4018
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 429
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918518
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918518 | QFN package and manufacturing process thereof | Jun 13, 2013 | Issued |
Array
(
[id] => 10863828
[patent_doc_number] => 08889526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-18
[patent_title] => 'Apparatus for thinning, testing and singulating a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 13/913674
[patent_app_country] => US
[patent_app_date] => 2013-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 3572
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913674
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/913674 | Apparatus for thinning, testing and singulating a semiconductor wafer | Jun 9, 2013 | Issued |
Array
(
[id] => 12969841
[patent_doc_number] => 09876189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-23
[patent_title] => Transparent electrode, electronic device, and transparent electrode manufacturing method
[patent_app_type] => utility
[patent_app_number] => 14/384878
[patent_app_country] => US
[patent_app_date] => 2013-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 25
[patent_no_of_words] => 25303
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14384878
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/384878 | Transparent electrode, electronic device, and transparent electrode manufacturing method | Apr 14, 2013 | Issued |
Array
(
[id] => 10189733
[patent_doc_number] => 09219164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-22
[patent_title] => 'Semiconductor device with oxide semiconductor channel'
[patent_app_type] => utility
[patent_app_number] => 13/860690
[patent_app_country] => US
[patent_app_date] => 2013-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 42
[patent_no_of_words] => 22406
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860690
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/860690 | Semiconductor device with oxide semiconductor channel | Apr 10, 2013 | Issued |
Array
(
[id] => 10165510
[patent_doc_number] => 09196743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-24
[patent_title] => 'Field effect device with oxide semiconductor layer'
[patent_app_type] => utility
[patent_app_number] => 13/860855
[patent_app_country] => US
[patent_app_date] => 2013-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 12078
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860855
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/860855 | Field effect device with oxide semiconductor layer | Apr 10, 2013 | Issued |