
Ajay Arora
Examiner (ID: 12666, Phone: (571)272-8347 , Office: P/2892 )
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2892, 2811 |
| Total Applications | 1272 |
| Issued Applications | 1029 |
| Pending Applications | 83 |
| Abandoned Applications | 184 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8224950
[patent_doc_number] => 20120139130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 13/372227
[patent_app_country] => US
[patent_app_date] => 2012-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 45
[patent_no_of_words] => 24839
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372227
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/372227 | Semiconductor device including a DC-DC converter | Feb 12, 2012 | Issued |
Array
(
[id] => 8289923
[patent_doc_number] => 20120178250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-12
[patent_title] => 'TESTING WIRING STRUCTURE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/353847
[patent_app_country] => US
[patent_app_date] => 2012-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4078
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353847
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/353847 | Testing wiring structure and method for forming the same | Jan 18, 2012 | Issued |
Array
(
[id] => 8139853
[patent_doc_number] => 20120094473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-19
[patent_title] => 'GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/336242
[patent_app_country] => US
[patent_app_date] => 2011-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 9602
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20120094473.pdf
[firstpage_image] =>[orig_patent_app_number] => 13336242
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/336242 | GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Dec 22, 2011 | Abandoned |
Array
(
[id] => 8897108
[patent_doc_number] => 08476630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-02
[patent_title] => 'Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon'
[patent_app_type] => utility
[patent_app_number] => 13/314327
[patent_app_country] => US
[patent_app_date] => 2011-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 3614
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314327
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/314327 | Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon | Dec 7, 2011 | Issued |
Array
(
[id] => 8237391
[patent_doc_number] => 20120146122
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-14
[patent_title] => '3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/315147
[patent_app_country] => US
[patent_app_date] => 2011-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5264
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315147
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/315147 | 3-D non-volatile memory device and method of manufacturing the same | Dec 7, 2011 | Issued |
Array
(
[id] => 8744942
[patent_doc_number] => 20130084659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'Testing Process for Semiconductor Devices'
[patent_app_type] => utility
[patent_app_number] => 13/312758
[patent_app_country] => US
[patent_app_date] => 2011-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5066
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13312758
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/312758 | Testing process for semiconductor devices | Dec 5, 2011 | Issued |
Array
(
[id] => 7815224
[patent_doc_number] => 20120061844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/302721
[patent_app_country] => US
[patent_app_date] => 2011-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12484
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20120061844.pdf
[firstpage_image] =>[orig_patent_app_number] => 13302721
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/302721 | COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Nov 21, 2011 | Abandoned |
Array
(
[id] => 8858489
[patent_doc_number] => 08461024
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-11
[patent_title] => 'Methods and apparatus for thinning, testing and singulating a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 13/292037
[patent_app_country] => US
[patent_app_date] => 2011-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 3545
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292037
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/292037 | Methods and apparatus for thinning, testing and singulating a semiconductor wafer | Nov 7, 2011 | Issued |
Array
(
[id] => 8742640
[patent_doc_number] => 20130082357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'PREFORMED TEXTURED SEMICONDUCTOR LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/253059
[patent_app_country] => US
[patent_app_date] => 2011-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3813
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253059
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253059 | PREFORMED TEXTURED SEMICONDUCTOR LAYER | Oct 3, 2011 | Abandoned |
Array
(
[id] => 10857368
[patent_doc_number] => 08883565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Separation of semiconductor devices from a wafer carrier'
[patent_app_type] => utility
[patent_app_number] => 13/252816
[patent_app_country] => US
[patent_app_date] => 2011-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 32
[patent_no_of_words] => 5906
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252816
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/252816 | Separation of semiconductor devices from a wafer carrier | Oct 3, 2011 | Issued |
Array
(
[id] => 9455147
[patent_doc_number] => 08716154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Reduced pattern loading using silicon oxide multi-layers'
[patent_app_type] => utility
[patent_app_number] => 13/251621
[patent_app_country] => US
[patent_app_date] => 2011-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6967
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251621
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/251621 | Reduced pattern loading using silicon oxide multi-layers | Oct 2, 2011 | Issued |
Array
(
[id] => 8134151
[patent_doc_number] => 20120091587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-19
[patent_title] => 'METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/251269
[patent_app_country] => US
[patent_app_date] => 2011-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 379
[patent_figures_cnt] => 379
[patent_no_of_words] => 73534
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20120091587.pdf
[firstpage_image] =>[orig_patent_app_number] => 13251269
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/251269 | Integrated circuit device and structure | Oct 1, 2011 | Issued |
Array
(
[id] => 8159407
[patent_doc_number] => 20120100695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-26
[patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/250957
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2736
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20120100695.pdf
[firstpage_image] =>[orig_patent_app_number] => 13250957
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250957 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Sep 29, 2011 | Abandoned |
Array
(
[id] => 8744951
[patent_doc_number] => 20130084668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'TEMPORARY ARC INDUCEMENT OF GLASS SUBSTRATE DURING DIFFUSIVE TRANSPORT DEPOSITION'
[patent_app_type] => utility
[patent_app_number] => 13/249892
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7910
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249892
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/249892 | TEMPORARY ARC INDUCEMENT OF GLASS SUBSTRATE DURING DIFFUSIVE TRANSPORT DEPOSITION | Sep 29, 2011 | Abandoned |
Array
(
[id] => 9355244
[patent_doc_number] => 08673777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-18
[patent_title] => 'In-line deposition system and process for deposition of a thin film layer'
[patent_app_type] => utility
[patent_app_number] => 13/249818
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6218
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249818
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/249818 | In-line deposition system and process for deposition of a thin film layer | Sep 29, 2011 | Issued |
Array
(
[id] => 8744971
[patent_doc_number] => 20130084688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'MULTI-LAYER PATTERN FOR ALTERNATE ALD PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 13/250937
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7312
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250937
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250937 | Multi-layer pattern for alternate ALD processes | Sep 29, 2011 | Issued |
Array
(
[id] => 8744967
[patent_doc_number] => 20130084685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'Methods for Ion Implantation'
[patent_app_type] => utility
[patent_app_number] => 13/250483
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3163
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250483
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250483 | Methods for Ion Implantation | Sep 29, 2011 | Abandoned |
Array
(
[id] => 8744997
[patent_doc_number] => 20130084714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'Method for Forming Single-Phase Multi-Element Film by PEALD'
[patent_app_type] => utility
[patent_app_number] => 13/250721
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250721
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250721 | Method for forming single-phase multi-element film by PEALD | Sep 29, 2011 | Issued |
Array
(
[id] => 8095017
[patent_doc_number] => 20120083111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'Methods of Manufacturing a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 13/249505
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7949
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20120083111.pdf
[firstpage_image] =>[orig_patent_app_number] => 13249505
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/249505 | Method of patterning a semiconductor device with hard mask | Sep 29, 2011 | Issued |
Array
(
[id] => 7728364
[patent_doc_number] => 20120013003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-19
[patent_title] => 'BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP'
[patent_app_type] => utility
[patent_app_number] => 13/244395
[patent_app_country] => US
[patent_app_date] => 2011-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5217
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20120013003.pdf
[firstpage_image] =>[orig_patent_app_number] => 13244395
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/244395 | BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP | Sep 23, 2011 | Abandoned |