Search

Ajay Ojha

Examiner (ID: 12382)

Most Active Art Unit
2824
Art Unit(s)
2824, 2898
Total Applications
990
Issued Applications
902
Pending Applications
19
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18751288 [patent_doc_number] => 11810606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Apparatus comprising one or more photonic memories [patent_app_type] => utility [patent_app_number] => 18/025624 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 30154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025624 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025624
Apparatus comprising one or more photonic memories Sep 20, 2021 Issued
Array ( [id] => 17339179 [patent_doc_number] => 20220005510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => CENTRALIZED PLACEMENT OF COMMAND AND ADDRESS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/448278 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448278
Centralized placement of command and address in memory devices Sep 20, 2021 Issued
Array ( [id] => 18040500 [patent_doc_number] => 20220384717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => CORE MAGNETIZATION REVERSAL METHOD OF SKYRMION AND DATA STORAGE DEVICE USING THE METHOD [patent_app_type] => utility [patent_app_number] => 17/469502 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469502
Core magnetization reversal method of skyrmion and data storage device using the method Sep 7, 2021 Issued
Array ( [id] => 17346861 [patent_doc_number] => 20220013192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MANAGING EXECUTION OF A SCRUB OPERATION IN VIEW OF AN OPERATING CHARACTERISTIC OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/467961 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467961
Managing execution of a scrub operation in view of an operating characteristic of a memory subsystem Sep 6, 2021 Issued
Array ( [id] => 18639249 [patent_doc_number] => 11763865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Signal receiver with skew-tolerant strobe gating [patent_app_type] => utility [patent_app_number] => 17/458215 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8466 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458215
Signal receiver with skew-tolerant strobe gating Aug 25, 2021 Issued
Array ( [id] => 18967207 [patent_doc_number] => 11900985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-13 [patent_title] => Clocking architecture supporting multiple data rates and reference edge selection [patent_app_type] => utility [patent_app_number] => 17/405527 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405527
Clocking architecture supporting multiple data rates and reference edge selection Aug 17, 2021 Issued
Array ( [id] => 18859136 [patent_doc_number] => 11856746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Well strap structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/403397 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403397
Well strap structures and methods of forming the same Aug 15, 2021 Issued
Array ( [id] => 18105317 [patent_doc_number] => 11545211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Semiconductor memory device and a method of operating the semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/400585 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 13592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400585
Semiconductor memory device and a method of operating the semiconductor memory device Aug 11, 2021 Issued
Array ( [id] => 18546781 [patent_doc_number] => 11720130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => On-chip power regulation system for MRAM operation [patent_app_type] => utility [patent_app_number] => 17/397542 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397542
On-chip power regulation system for MRAM operation Aug 8, 2021 Issued
Array ( [id] => 17886140 [patent_doc_number] => 20220301617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => DATA PROCESSING CIRCUIT AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/396743 [patent_app_country] => US [patent_app_date] => 2021-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396743
Data processing circuit and device Aug 7, 2021 Issued
Array ( [id] => 17246817 [patent_doc_number] => 20210366562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => MEMORY SYSTEM PROCESSING REQUEST BASED ON INFERENCE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/395872 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395872
Memory system processing request based on inference and operating method of the same Aug 5, 2021 Issued
Array ( [id] => 17231972 [patent_doc_number] => 20210358529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE AND MEMORY CONTROLLER THEREFOR [patent_app_type] => utility [patent_app_number] => 17/387036 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387036
Dynamic random access memory (DRAM) device and memory controller therefor Jul 27, 2021 Issued
Array ( [id] => 17217522 [patent_doc_number] => 20210350860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => DYNAMIC REFERENCE CURRENT MEMORY ARRAY AND METHOD [patent_app_type] => utility [patent_app_number] => 17/383089 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/383089
Dynamic reference current memory array and method Jul 21, 2021 Issued
Array ( [id] => 18918970 [patent_doc_number] => 11881258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Apparatus and related method to indicate stability and instability in bit cell [patent_app_type] => utility [patent_app_number] => 17/377769 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5807 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377769
Apparatus and related method to indicate stability and instability in bit cell Jul 15, 2021 Issued
Array ( [id] => 17373393 [patent_doc_number] => 20220028445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => IN-MEMORY COMPUTING DEVICE SUPPORTING ARITHMETIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/377766 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377766
In-memory computing device supporting arithmetic operations Jul 15, 2021 Issued
Array ( [id] => 17318504 [patent_doc_number] => 20210407554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/376090 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376090
SEMICONDUCTOR DEVICE Jul 13, 2021 Abandoned
Array ( [id] => 17188519 [patent_doc_number] => 20210335404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/368652 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368652
Memory controller and method of operating the same Jul 5, 2021 Issued
Array ( [id] => 17971136 [patent_doc_number] => 11488683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Device for detecting margin of circuit operating at certain speed [patent_app_type] => utility [patent_app_number] => 17/368436 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4103 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368436
Device for detecting margin of circuit operating at certain speed Jul 5, 2021 Issued
Array ( [id] => 17187754 [patent_doc_number] => 20210334639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => PROGRAMMABLE OUTPUT BLOCKS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/367542 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367542
Programmable output blocks for analog neural memory in a deep learning artificial neural network Jul 4, 2021 Issued
Array ( [id] => 17462294 [patent_doc_number] => 20220075599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/365034 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365034
Memory device and operation method thereof Jun 30, 2021 Issued
Menu