Search

Akash Saxena

Examiner (ID: 7182, Phone: (571)272-8351 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2147, 2128, 2188
Total Applications
670
Issued Applications
281
Pending Applications
77
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20447421 [patent_doc_number] => 20260004143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP [patent_app_type] => utility [patent_app_number] => 19/257390 [patent_app_country] => US [patent_app_date] => 2025-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19257390 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/257390
REINFORCED LEARNING FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP Jun 30, 2025 Pending
Array ( [id] => 19899449 [patent_doc_number] => 12277373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-15 [patent_title] => System and computer-readable medium for improving the critical path delay of a FPGA routing tool at smaller channel widths [patent_app_type] => utility [patent_app_number] => 18/793209 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/793209
System and computer-readable medium for improving the critical path delay of a FPGA routing tool at smaller channel widths Aug 1, 2024 Issued
Array ( [id] => 19581751 [patent_doc_number] => 12147872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Quantum noise process analysis method and apparatus, device, and storage medium [patent_app_type] => utility [patent_app_number] => 18/538946 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538946
Quantum noise process analysis method and apparatus, device, and storage medium Dec 12, 2023 Issued
Array ( [id] => 18864137 [patent_doc_number] => 20230418573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/466589 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466589
CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION Sep 12, 2023 Abandoned
Array ( [id] => 18954560 [patent_doc_number] => 20240042887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => VEHICLE CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/446935 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446935
VEHICLE CHARGING SYSTEM Aug 8, 2023 Pending
Array ( [id] => 18788234 [patent_doc_number] => 20230376665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/230405 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230405
SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT Aug 3, 2023 Pending
Array ( [id] => 19144950 [patent_doc_number] => 20240143886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => METHOD OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESS USING MACHINE LEARNING, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND LAYOUT CORRECTION SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/342011 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342011
METHOD OF CORRECTING LAYOUT FOR SEMICONDUCTOR PROCESS USING MACHINE LEARNING, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND LAYOUT CORRECTION SYSTEM PERFORMING THE SAME Jun 26, 2023 Pending
Array ( [id] => 19602796 [patent_doc_number] => 20240393676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => DESIGN METHOD OF PHOTOMASK STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/334382 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334382
DESIGN METHOD OF PHOTOMASK STRUCTURE Jun 13, 2023 Pending
Array ( [id] => 18728242 [patent_doc_number] => 20230342535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/333259 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333259
Integrated circuit, system and method of forming the same Jun 11, 2023 Issued
Array ( [id] => 19493399 [patent_doc_number] => 12112115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Routing structure and method of wafer substrate with standard integration zone for integration on-wafer [patent_app_type] => utility [patent_app_number] => 18/328800 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3686 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328800
Routing structure and method of wafer substrate with standard integration zone for integration on-wafer Jun 4, 2023 Issued
Array ( [id] => 19006292 [patent_doc_number] => 20240070363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHOD AND APPARATUS FOR SIMULATING AN ELECTRICAL CIRCUIT, DIGITAL REAL-TIME SIMULATOR, COMPUTER PROGRAM AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/328147 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328147
METHOD AND APPARATUS FOR SIMULATING AN ELECTRICAL CIRCUIT, DIGITAL REAL-TIME SIMULATOR, COMPUTER PROGRAM AND COMPUTER-READABLE MEDIUM Jun 1, 2023 Pending
Array ( [id] => 18651923 [patent_doc_number] => 20230297759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/323593 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323593
Integrated circuit stack verification method and system for performing the same May 24, 2023 Issued
Array ( [id] => 18811162 [patent_doc_number] => 20230385498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FAULT DIAGNOSTICS [patent_app_type] => utility [patent_app_number] => 18/303219 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303219
Fault diagnostics Apr 18, 2023 Issued
Array ( [id] => 19514667 [patent_doc_number] => 20240346353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SCALABLE ANALOG ZERO NOISE EXTRAPOLATION BY ECHO EXTENSION [patent_app_type] => utility [patent_app_number] => 18/299178 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299178
SCALABLE ANALOG ZERO NOISE EXTRAPOLATION BY ECHO EXTENSION Apr 11, 2023 Pending
Array ( [id] => 19514531 [patent_doc_number] => 20240346217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR CORE-ONLY DESIGN [patent_app_type] => utility [patent_app_number] => 18/299427 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299427
SEMICONDUCTOR STRUCTURE AND METHOD FOR CORE-ONLY DESIGN Apr 11, 2023 Pending
Array ( [id] => 18811170 [patent_doc_number] => 20230385506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN SYSTEM USING PARTITIONING AND DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN METHOD USING PARTITIONING [patent_app_type] => utility [patent_app_number] => 18/296440 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296440
DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN SYSTEM USING PARTITIONING AND DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN METHOD USING PARTITIONING Apr 5, 2023 Pending
Array ( [id] => 18651044 [patent_doc_number] => 20230296880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => RESIST MODELING METHOD FOR ANGLED GRATINGS [patent_app_type] => utility [patent_app_number] => 18/123085 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123085
RESIST MODELING METHOD FOR ANGLED GRATINGS Mar 16, 2023 Pending
Array ( [id] => 18651910 [patent_doc_number] => 20230297746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => LAYOUT DESIGN TOOL [patent_app_type] => utility [patent_app_number] => 18/184902 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184902
LAYOUT DESIGN TOOL Mar 15, 2023 Pending
Array ( [id] => 18470807 [patent_doc_number] => 20230205093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD OF MANUFACTURING PHOTO MASKS [patent_app_type] => utility [patent_app_number] => 18/114845 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114845
METHOD OF MANUFACTURING PHOTO MASKS Feb 26, 2023 Abandoned
Array ( [id] => 18599268 [patent_doc_number] => 20230274068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING [patent_app_type] => utility [patent_app_number] => 18/110338 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110338
PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING Feb 14, 2023 Pending
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