
Alan D. Diamond
Examiner (ID: 5380, Phone: (571)272-1338 , Office: P/3991 )
| Most Active Art Unit | 1753 |
| Art Unit(s) | 1751, 1629, 3991, 1111, 1753, 1736 |
| Total Applications | 2039 |
| Issued Applications | 1465 |
| Pending Applications | 300 |
| Abandoned Applications | 284 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13682365
[patent_doc_number] => 20160379919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => Electronic device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/187818
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2750
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187818
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/187818 | Electronic device and method of manufacturing the same | Jun 20, 2016 | Abandoned |
Array
(
[id] => 11918489
[patent_doc_number] => 09786681
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-10
[patent_title] => 'Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure'
[patent_app_type] => utility
[patent_app_number] => 15/186768
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 34
[patent_no_of_words] => 15313
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186768
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186768 | Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure | Jun 19, 2016 | Issued |
Array
(
[id] => 11557703
[patent_doc_number] => 20170103948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-13
[patent_title] => 'INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/186825
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 51
[patent_no_of_words] => 19002
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186825
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186825 | Integrated circuit device and method of fabricating the same | Jun 19, 2016 | Issued |
Array
(
[id] => 11475549
[patent_doc_number] => 20170062332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/186734
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8028
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186734
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186734 | Semiconductor device | Jun 19, 2016 | Issued |
Array
(
[id] => 13709507
[patent_doc_number] => 20170365708
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => TRENCH POWER SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/186685
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186685
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186685 | Trench power semiconductor device | Jun 19, 2016 | Issued |
Array
(
[id] => 11904364
[patent_doc_number] => 09773805
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-09-26
[patent_title] => 'Integrated structures and methods of forming integrated structures'
[patent_app_type] => utility
[patent_app_number] => 15/187632
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4531
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187632
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/187632 | Integrated structures and methods of forming integrated structures | Jun 19, 2016 | Issued |
Array
(
[id] => 13112137
[patent_doc_number] => 10074729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-11
[patent_title] => Forming highly conductive source/drain contacts in III-Nitride transistors
[patent_app_type] => utility
[patent_app_number] => 15/170506
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2629
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170506
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/170506 | Forming highly conductive source/drain contacts in III-Nitride transistors | May 31, 2016 | Issued |
Array
(
[id] => 11652996
[patent_doc_number] => 20170148897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'VERTICAL TRANSISTOR WITH AIR-GAP SPACER'
[patent_app_type] => utility
[patent_app_number] => 15/163049
[patent_app_country] => US
[patent_app_date] => 2016-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5591
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163049
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/163049 | Vertical transistor with air-gap spacer | May 23, 2016 | Issued |
Array
(
[id] => 11652975
[patent_doc_number] => 20170148876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'VERTICAL TRANSISTOR WITH AIR-GAP SPACER'
[patent_app_type] => utility
[patent_app_number] => 15/163059
[patent_app_country] => US
[patent_app_date] => 2016-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5607
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163059
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/163059 | Vertical transistor with air-gap spacer | May 23, 2016 | Issued |
Array
(
[id] => 12779932
[patent_doc_number] => 20180151812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => OLED DISPLAY DEVICE and MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/120742
[patent_app_country] => US
[patent_app_date] => 2016-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4941
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15120742
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/120742 | OLED DISPLAY DEVICE and MANUFACTURING METHOD THEREOF | May 18, 2016 | Abandoned |
Array
(
[id] => 11043182
[patent_doc_number] => 20160240137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-18
[patent_title] => 'DISPLAY DEVICE AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/139791
[patent_app_country] => US
[patent_app_date] => 2016-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 12107
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139791
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/139791 | Display device and electronic apparatus | Apr 26, 2016 | Issued |
Array
(
[id] => 11733159
[patent_doc_number] => 20170194602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'Display Substrate and Manufacturing Method Therefor, and Display Device'
[patent_app_type] => utility
[patent_app_number] => 15/321211
[patent_app_country] => US
[patent_app_date] => 2016-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5420
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15321211
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/321211 | Display substrate and manufacturing method therefor, and display device | Apr 11, 2016 | Issued |
Array
(
[id] => 11028922
[patent_doc_number] => 20160225878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-04
[patent_title] => 'Method of Forming A Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array'
[patent_app_type] => utility
[patent_app_number] => 15/091202
[patent_app_country] => US
[patent_app_date] => 2016-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2462
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091202
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/091202 | Method of forming a self-aligned stack gate structure for use in a non-volatile memory array | Apr 4, 2016 | Issued |
Array
(
[id] => 11014406
[patent_doc_number] => 20160211359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'Integrated Power Device'
[patent_app_type] => utility
[patent_app_number] => 15/083595
[patent_app_country] => US
[patent_app_date] => 2016-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1469
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083595
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/083595 | Integrated power device | Mar 28, 2016 | Issued |
Array
(
[id] => 11599915
[patent_doc_number] => 09647093
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Fin cut for taper device'
[patent_app_type] => utility
[patent_app_number] => 15/073065
[patent_app_country] => US
[patent_app_date] => 2016-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 42
[patent_no_of_words] => 4728
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073065
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/073065 | Fin cut for taper device | Mar 16, 2016 | Issued |
Array
(
[id] => 11273523
[patent_doc_number] => 20160336067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-17
[patent_title] => 'NON-VOLATILE COMPOSITE NANOSCOPIC FABRIC NAND MEMORY ARRAYS AND METHODS OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 15/069336
[patent_app_country] => US
[patent_app_date] => 2016-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 275
[patent_figures_cnt] => 275
[patent_no_of_words] => 127711
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069336
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/069336 | Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same | Mar 13, 2016 | Issued |
Array
(
[id] => 11307803
[patent_doc_number] => 09515209
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-06
[patent_title] => 'Bare quantum dots superlattice photonic devices'
[patent_app_type] => utility
[patent_app_number] => 15/068076
[patent_app_country] => US
[patent_app_date] => 2016-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 30
[patent_no_of_words] => 12315
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 493
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068076
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/068076 | Bare quantum dots superlattice photonic devices | Mar 10, 2016 | Issued |
Array
(
[id] => 13201819
[patent_doc_number] => 10115832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Thin film transistor, method for manufacturing the same, array substrate and display device
[patent_app_type] => utility
[patent_app_number] => 15/317251
[patent_app_country] => US
[patent_app_date] => 2016-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5722
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15317251
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/317251 | Thin film transistor, method for manufacturing the same, array substrate and display device | Feb 23, 2016 | Issued |
Array
(
[id] => 10828201
[patent_doc_number] => 20160174371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'METHOD FOR MAKING ELECTRONIC DEVICE WITH COVER LAYER WITH OPENINGS AND RELATED DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/049363
[patent_app_country] => US
[patent_app_date] => 2016-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2881
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049363
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/049363 | Method for making electronic device with cover layer with openings and related devices | Feb 21, 2016 | Issued |
Array
(
[id] => 12141261
[patent_doc_number] => 20180019343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/548123
[patent_app_country] => US
[patent_app_date] => 2016-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 45
[patent_no_of_words] => 48777
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15548123
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/548123 | Semiconductor device and manufacturing method thereof | Jan 27, 2016 | Issued |