
Alan Otto
Examiner (ID: 15425, Phone: (571)270-1626 , Office: P/2132 )
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2132, 2182, 2187 |
| Total Applications | 463 |
| Issued Applications | 304 |
| Pending Applications | 32 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10286289
[patent_doc_number] => 20150171287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'RESIN SHEET LAMINATE AND PROCESS FOR PRODUCING SEMICONDUCTOR LIGHT-EMITTING ELEMENT USING SAME'
[patent_app_type] => utility
[patent_app_number] => 14/407307
[patent_app_country] => US
[patent_app_date] => 2013-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12498
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14407307
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/407307 | RESIN SHEET LAMINATE AND PROCESS FOR PRODUCING SEMICONDUCTOR LIGHT-EMITTING ELEMENT USING SAME | Jun 12, 2013 | Abandoned |
Array
(
[id] => 10638614
[patent_doc_number] => 09356127
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-31
[patent_title] => 'Layout structure of heterojunction bipolar transistors'
[patent_app_type] => utility
[patent_app_number] => 13/913290
[patent_app_country] => US
[patent_app_date] => 2013-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4427
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913290
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/913290 | Layout structure of heterojunction bipolar transistors | Jun 6, 2013 | Issued |
Array
(
[id] => 9188831
[patent_doc_number] => 20130328146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-12
[patent_title] => 'TRANSVERSELY-ILLUMINATED HIGH CURRENT PHOTOCONDUCTIVE SWITCHES WITH GEOMETRY-CONSTRAINED CONDUCTIVITY PATH'
[patent_app_type] => utility
[patent_app_number] => 13/912137
[patent_app_country] => US
[patent_app_date] => 2013-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3834
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912137
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/912137 | Transversely-illuminated high current photoconductive switches with geometry-constrained conductivity path | Jun 5, 2013 | Issued |
Array
(
[id] => 9188743
[patent_doc_number] => 20130328058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-12
[patent_title] => 'Transversely-illuminated high current photoconductive switches with geometry-constrained conductivity path'
[patent_app_type] => utility
[patent_app_number] => 13/912162
[patent_app_country] => US
[patent_app_date] => 2013-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3834
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912162
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/912162 | Transversely-illuminated high current photoconductive switches with geometry-constrained conductivity path | Jun 5, 2013 | Abandoned |
Array
(
[id] => 9396629
[patent_doc_number] => 20140094035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-03
[patent_title] => 'CARBON DEPOSITION-ETCH-ASH GAP FILL PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/896729
[patent_app_country] => US
[patent_app_date] => 2013-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7250
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896729
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/896729 | Carbon deposition-etch-ash gap fill process | May 16, 2013 | Issued |
Array
(
[id] => 9041774
[patent_doc_number] => 20130244412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-19
[patent_title] => 'REPLACEMENT METAL GATE TRANSISTORS WITH REDUCED GATE OXIDE LEAKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/873761
[patent_app_country] => US
[patent_app_date] => 2013-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3232
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13873761
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/873761 | Replacement metal gate transistors with reduced gate oxide leakage | Apr 29, 2013 | Issued |
Array
(
[id] => 10919873
[patent_doc_number] => 20140322892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-30
[patent_title] => 'MULTI-WAFER PAIR ANODIC BONDING APPARATUS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/872632
[patent_app_country] => US
[patent_app_date] => 2013-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6218
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872632
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/872632 | Multi-wafer pair anodic bonding apparatus and method | Apr 28, 2013 | Issued |
Array
(
[id] => 10905768
[patent_doc_number] => 20140308782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-16
[patent_title] => 'SELF-LIMITING SELECTIVE EPITAXY PROCESS FOR PREVENTING MERGER OF SEMICONDUCTOR FINS'
[patent_app_type] => utility
[patent_app_number] => 13/862759
[patent_app_country] => US
[patent_app_date] => 2013-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5989
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862759
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/862759 | Self-limiting selective epitaxy process for preventing merger of semiconductor fins | Apr 14, 2013 | Issued |
Array
(
[id] => 9013967
[patent_doc_number] => 20130228931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-05
[patent_title] => 'SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/861598
[patent_app_country] => US
[patent_app_date] => 2013-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4415
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13861598
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/861598 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS | Apr 11, 2013 | Abandoned |
Array
(
[id] => 8987036
[patent_doc_number] => 20130214317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-22
[patent_title] => 'NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/764228
[patent_app_country] => US
[patent_app_date] => 2013-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3592
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764228
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/764228 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME | Feb 10, 2013 | Abandoned |
Array
(
[id] => 10189736
[patent_doc_number] => 09219168
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-22
[patent_title] => 'Non-volatile memory device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/737411
[patent_app_country] => US
[patent_app_date] => 2013-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 7361
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737411
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/737411 | Non-volatile memory device and method of manufacturing the same | Jan 8, 2013 | Issued |
Array
(
[id] => 8717843
[patent_doc_number] => 20130069060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/677504
[patent_app_country] => US
[patent_app_date] => 2012-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8719
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677504
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/677504 | Semiconductor device and method for manufacturing the same | Nov 14, 2012 | Issued |
Array
(
[id] => 9631820
[patent_doc_number] => 20140209928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'LIGHT SOURCE ASSEMBLY AND A PROCESS FOR PRODUCING A LIGHT SOURCE ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 14/346717
[patent_app_country] => US
[patent_app_date] => 2012-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7242
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14346717
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/346717 | LIGHT SOURCE ASSEMBLY AND A PROCESS FOR PRODUCING A LIGHT SOURCE ASSEMBLY | Sep 20, 2012 | Abandoned |
Array
(
[id] => 10597460
[patent_doc_number] => 09318555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'Fabrication of graphene nanoelectronic devices on SOI structures'
[patent_app_type] => utility
[patent_app_number] => 13/611923
[patent_app_country] => US
[patent_app_date] => 2012-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 3440
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611923
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/611923 | Fabrication of graphene nanoelectronic devices on SOI structures | Sep 11, 2012 | Issued |
Array
(
[id] => 8647079
[patent_doc_number] => 20130032809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same'
[patent_app_type] => utility
[patent_app_number] => 13/605324
[patent_app_country] => US
[patent_app_date] => 2012-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9591
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605324
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/605324 | Semiconductor devices with non-implanted barrier regions and methods of fabricating same | Sep 5, 2012 | Issued |
Array
(
[id] => 8499541
[patent_doc_number] => 20120298949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-29
[patent_title] => 'Graphene/Nanostructure FET with Self-Aligned Contact and Gate'
[patent_app_type] => utility
[patent_app_number] => 13/570275
[patent_app_country] => US
[patent_app_date] => 2012-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2454
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570275
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/570275 | Graphene/Nanostructure FET with Self-Aligned Contact and Gate | Aug 8, 2012 | Abandoned |
Array
(
[id] => 9832421
[patent_doc_number] => 08941240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-27
[patent_title] => 'Fabricating a contact rhodium structure by electroplating and electroplating composition'
[patent_app_type] => utility
[patent_app_number] => 13/564414
[patent_app_country] => US
[patent_app_date] => 2012-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 4221
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564414
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/564414 | Fabricating a contact rhodium structure by electroplating and electroplating composition | Jul 31, 2012 | Issued |
Array
(
[id] => 10870176
[patent_doc_number] => 08895372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'Graphene based three-dimensional integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 13/557501
[patent_app_country] => US
[patent_app_date] => 2012-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 2667
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557501
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/557501 | Graphene based three-dimensional integrated circuit device | Jul 24, 2012 | Issued |
Array
(
[id] => 8474374
[patent_doc_number] => 20120273780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/547377
[patent_app_country] => US
[patent_app_date] => 2012-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 28173
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547377
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/547377 | Semiconductor device and method for manufacturing the same | Jul 11, 2012 | Issued |
Array
(
[id] => 8391840
[patent_doc_number] => 20120229684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-13
[patent_title] => 'IMAGE SENSOR WITH RAISED PHOTOSENSITIVE ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 13/473307
[patent_app_country] => US
[patent_app_date] => 2012-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5664
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13473307
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/473307 | Image sensor with raised photosensitive elements | May 15, 2012 | Issued |