
Alan Otto
Examiner (ID: 14125)
| Most Active Art Unit | 2132 |
| Art Unit(s) | 2187, 2132, 2182 |
| Total Applications | 469 |
| Issued Applications | 306 |
| Pending Applications | 34 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 596346
[patent_doc_number] => 07454589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Data buffer circuit, interface circuit and control method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/102656
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11807
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/454/07454589.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102656
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102656 | Data buffer circuit, interface circuit and control method therefor | Apr 10, 2005 | Issued |
Array
(
[id] => 7232927
[patent_doc_number] => 20050262297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Disk drive connected to host system via memory interface circuit, and interface connecting method'
[patent_app_type] => utility
[patent_app_number] => 11/102734
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7358
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20050262297.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102734
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102734 | Disk drive connected to host system via memory interface circuit, and interface connecting method | Apr 10, 2005 | Abandoned |
Array
(
[id] => 5861631
[patent_doc_number] => 20060230245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Data storage safety indicator and expander'
[patent_app_type] => utility
[patent_app_number] => 11/101589
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5892
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20060230245.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101589
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101589 | Data storage safety indicator and expander | Apr 7, 2005 | Abandoned |
Array
(
[id] => 5728537
[patent_doc_number] => 20060059298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Memory module with memory devices of different capacity'
[patent_app_type] => utility
[patent_app_number] => 11/102181
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5355
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20060059298.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102181
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102181 | Memory module with memory devices of different capacity | Apr 7, 2005 | Abandoned |
Array
(
[id] => 7692967
[patent_doc_number] => 20070016719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Memory device including nonvolatile memory and memory controller'
[patent_app_type] => utility
[patent_app_number] => 11/101440
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5660
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20070016719.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101440
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101440 | Memory device including nonvolatile memory and memory controller | Apr 7, 2005 | Abandoned |
Array
(
[id] => 96872
[patent_doc_number] => 07734888
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-06-08
[patent_title] => 'Capacity guarantees in a storage system'
[patent_app_type] => utility
[patent_app_number] => 11/101909
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5801
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/734/07734888.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101909
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101909 | Capacity guarantees in a storage system | Apr 7, 2005 | Issued |
Array
(
[id] => 5861632
[patent_doc_number] => 20060230246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Memory allocation technique using memory resource groups'
[patent_app_type] => utility
[patent_app_number] => 11/102077
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4308
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20060230246.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102077
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102077 | Memory allocation technique using memory resource groups | Apr 7, 2005 | Abandoned |
Array
(
[id] => 5861622
[patent_doc_number] => 20060230236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Method and apparatus for precognitive fetching'
[patent_app_type] => utility
[patent_app_number] => 11/102339
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5575
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20060230236.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102339
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102339 | Method and apparatus for precognitive fetching | Apr 7, 2005 | Abandoned |
Array
(
[id] => 5861621
[patent_doc_number] => 20060230235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Low locality-of-reference support in a multi-level cache hierachy'
[patent_app_type] => utility
[patent_app_number] => 11/101785
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2493
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20060230235.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101785
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101785 | Low locality-of-reference support in a multi-level cache hierachy | Apr 6, 2005 | Issued |
Array
(
[id] => 860373
[patent_doc_number] => 07376798
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-05-20
[patent_title] => 'Memory management methods and systems that support cache consistency'
[patent_app_type] => utility
[patent_app_number] => 11/102127
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5491
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/376/07376798.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102127
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102127 | Memory management methods and systems that support cache consistency | Apr 6, 2005 | Issued |
Array
(
[id] => 4440857
[patent_doc_number] => 07971002
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-06-28
[patent_title] => 'Maintaining instruction coherency in a translation-based computer system architecture'
[patent_app_type] => utility
[patent_app_number] => 11/102538
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3816
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/971/07971002.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102538
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102538 | Maintaining instruction coherency in a translation-based computer system architecture | Apr 6, 2005 | Issued |
Array
(
[id] => 9527462
[patent_doc_number] => 08751753
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-06-10
[patent_title] => 'Coherence de-coupling buffer'
[patent_app_type] => utility
[patent_app_number] => 11/102171
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3295
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11102171
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102171 | Coherence de-coupling buffer | Apr 6, 2005 | Issued |
Array
(
[id] => 7047019
[patent_doc_number] => 20050251614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Processer'
[patent_app_type] => utility
[patent_app_number] => 11/100490
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 12262
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0251/20050251614.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100490
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100490 | Processor to reduce data rearrangement instructions for matrices in multiple memory banks | Apr 6, 2005 | Issued |
Array
(
[id] => 6953870
[patent_doc_number] => 20050228965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Method and device for calculating addresses of a segmented program memory'
[patent_app_type] => utility
[patent_app_number] => 11/101355
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2378
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20050228965.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101355
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101355 | Method and device for calculating addresses of a segmented program memory | Apr 6, 2005 | Issued |
Array
(
[id] => 5638930
[patent_doc_number] => 20060069904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Information processing apparatus and startup control method'
[patent_app_type] => utility
[patent_app_number] => 11/101965
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2633
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0069/20060069904.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101965
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101965 | Information processing apparatus and startup control method | Apr 6, 2005 | Abandoned |
Array
(
[id] => 366557
[patent_doc_number] => 07484061
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-27
[patent_title] => 'Method for performing swap operation and apparatus for implementing the same'
[patent_app_type] => utility
[patent_app_number] => 11/100976
[patent_app_country] => US
[patent_app_date] => 2005-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4654
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/484/07484061.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100976
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100976 | Method for performing swap operation and apparatus for implementing the same | Apr 5, 2005 | Issued |
| 11/100134 | Systems and methods for memory access | Apr 5, 2005 | Abandoned |
Array
(
[id] => 6968205
[patent_doc_number] => 20050235102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Memory controller, semiconductor integrated circuit device, microcomputer, and electronic equipment'
[patent_app_type] => utility
[patent_app_number] => 11/100230
[patent_app_country] => US
[patent_app_date] => 2005-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5502
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20050235102.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100230
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100230 | Memory controller, semiconductor integrated circuit device, microcomputer, and electronic equipment | Apr 5, 2005 | Abandoned |
Array
(
[id] => 873403
[patent_doc_number] => 07366828
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-29
[patent_title] => 'Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/100228
[patent_app_country] => US
[patent_app_date] => 2005-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3952
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/366/07366828.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100228 | Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device | Apr 5, 2005 | Issued |
Array
(
[id] => 6927470
[patent_doc_number] => 20050240727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-27
[patent_title] => 'Method and system for managing storage area networks'
[patent_app_type] => utility
[patent_app_number] => 11/099751
[patent_app_country] => US
[patent_app_date] => 2005-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 3737
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0240/20050240727.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099751
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099751 | Method and system for managing storage area networks | Apr 5, 2005 | Abandoned |