Search

Albert Davis Jr.

Examiner (ID: 5456)

Most Active Art Unit
3406
Art Unit(s)
3406, 3405, 3102, 2899, 3407
Total Applications
1496
Issued Applications
1404
Pending Applications
2
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18439706 [patent_doc_number] => 20230187001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MEMORY DEVICES WITH DYNAMIC PROGRAM VERIFY LEVELS [patent_app_type] => utility [patent_app_number] => 18/107200 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107200
Memory devices with dynamic program verify levels Feb 7, 2023 Issued
Array ( [id] => 19720093 [patent_doc_number] => 12205636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Write assist circuit for static random-access memory (SRAM) [patent_app_type] => utility [patent_app_number] => 18/163584 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6391 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163584
Write assist circuit for static random-access memory (SRAM) Feb 1, 2023 Issued
Array ( [id] => 18905756 [patent_doc_number] => 20240021241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DRIVE CIRCUIT WITH IMPROVED TIMING MARGIN FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/103364 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103364 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103364
Drive circuit with improved timing margin for memory device Jan 29, 2023 Issued
Array ( [id] => 19314218 [patent_doc_number] => 12040042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor device including transistor [patent_app_type] => utility [patent_app_number] => 18/101140 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 59 [patent_no_of_words] => 26146 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101140
Semiconductor device including transistor Jan 24, 2023 Issued
Array ( [id] => 18555003 [patent_doc_number] => 20230253019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MEMORY DEVICE SUPPORTING IN-MEMORY MAC OPERATION BETWEEN TERNARY INPUT DATA AND BINARY WEIGHT USING CHARGE SHARING METHOD AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/101287 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101287
Memory device supporting in-memory MAC operation between ternary input data and binary weight using charge sharing method and operation method thereof Jan 24, 2023 Issued
Array ( [id] => 19670636 [patent_doc_number] => 12183403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Three-dimensional memory device and improved methods of reading the same by shortening read times [patent_app_type] => utility [patent_app_number] => 18/156955 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 8733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156955
Three-dimensional memory device and improved methods of reading the same by shortening read times Jan 18, 2023 Issued
Array ( [id] => 19740981 [patent_doc_number] => 12217820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Counter circuit [patent_app_type] => utility [patent_app_number] => 18/155900 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 13978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155900
Counter circuit Jan 17, 2023 Issued
Array ( [id] => 18781987 [patent_doc_number] => 11823752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Memory devices for program verify operations [patent_app_type] => utility [patent_app_number] => 18/095711 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 15219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095711
Memory devices for program verify operations Jan 10, 2023 Issued
Array ( [id] => 18394572 [patent_doc_number] => 20230162793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS [patent_app_type] => utility [patent_app_number] => 18/095049 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095049
Memory devices with four data line bias levels Jan 9, 2023 Issued
Array ( [id] => 20274661 [patent_doc_number] => 12444445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Controller, memory device and control method for adjusting power consumption [patent_app_type] => utility [patent_app_number] => 18/147007 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/147007
Controller, memory device and control method for adjusting power consumption Dec 27, 2022 Issued
Array ( [id] => 20404254 [patent_doc_number] => 12494234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Managing data transfer in semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/077557 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10444 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077557 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077557
Managing data transfer in semiconductor devices Dec 7, 2022 Issued
Array ( [id] => 18472746 [patent_doc_number] => 20230207034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SEMICONDUCTOR DEVICE AND TESTING METHOD FOR MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/062262 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062262
SEMICONDUCTOR DEVICE AND TESTING METHOD FOR MEMORY CIRCUIT Dec 5, 2022 Pending
Array ( [id] => 19205871 [patent_doc_number] => 20240177770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => NON-VOLATILE MEMORY STRUCTURE WITH SINGLE CELL OR TWIN CELL SENSING [patent_app_type] => utility [patent_app_number] => 18/058992 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058992
NON-VOLATILE MEMORY STRUCTURE WITH SINGLE CELL OR TWIN CELL SENSING Nov 27, 2022 Pending
Array ( [id] => 18239976 [patent_doc_number] => 20230072287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => RRAM CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/054359 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054359
RRAM circuit Nov 9, 2022 Issued
Array ( [id] => 19399496 [patent_doc_number] => 12073882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/975609 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975609
Semiconductor memory device Oct 27, 2022 Issued
Array ( [id] => 18943152 [patent_doc_number] => 20240038291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => SELECTABLE ROW HAMMER MITIGATION [patent_app_type] => utility [patent_app_number] => 17/973726 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973726
Selectable row hammer mitigation Oct 25, 2022 Issued
Array ( [id] => 19942441 [patent_doc_number] => 12314572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Conflict detection and address arbitration for routing scatter and gather transactions for a memory bank [patent_app_type] => utility [patent_app_number] => 17/962683 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962683
Conflict detection and address arbitration for routing scatter and gather transactions for a memory bank Oct 9, 2022 Issued
Array ( [id] => 20111260 [patent_doc_number] => 12361995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Spin-orbit-torque (SOT) MRAM with doubled layer of SOT metal [patent_app_type] => utility [patent_app_number] => 17/956938 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956938
Spin-orbit-torque (SOT) MRAM with doubled layer of SOT metal Sep 29, 2022 Issued
Array ( [id] => 18394578 [patent_doc_number] => 20230162799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/956225 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956225
Storage controller and storage device including the same Sep 28, 2022 Issued
Array ( [id] => 19654255 [patent_doc_number] => 12176055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Data receiving circuit, data receiving system, and memory device [patent_app_type] => utility [patent_app_number] => 17/936107 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 16905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936107
Data receiving circuit, data receiving system, and memory device Sep 27, 2022 Issued
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