Albert Decady

Array ( [id] => 3897574 [patent_doc_number] => 05748871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Dual bus architecture for a storage device' [patent_app_type] => 1 [patent_app_number] => 8/514479 [patent_app_country] => US [patent_app_date] => 1995-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3659 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748871.pdf [firstpage_image] =>[orig_patent_app_number] => 514479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707134 [patent_doc_number] => 05680538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'System and method for maintaining a minimum quality of service during read operations on disk arrays' [patent_app_type] => 1 [patent_app_number] => 8/513644 [patent_app_country] => US [patent_app_date] => 1995-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5126 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680538.pdf [firstpage_image] =>[orig_patent_app_number] => 513644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3735530 [patent_doc_number] => 05701408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method for testing computer operating or application programming interfaces' [patent_app_type] => 1 [patent_app_number] => 8/500276 [patent_app_country] => US [patent_app_date] => 1995-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2523 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701408.pdf [firstpage_image] =>[orig_patent_app_number] => 500276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3715909 [patent_doc_number] => 05675730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method and apparatus for extensible type-specific data presentation by a debugger' [patent_app_type] => 1 [patent_app_number] => 8/499715 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3832 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675730.pdf [firstpage_image] =>[orig_patent_app_number] => 499715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3587250 [patent_doc_number] => 05524116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Packet framer' [patent_app_type] => 1 [patent_app_number] => 8/497189 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4418 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524116.pdf [firstpage_image] =>[orig_patent_app_number] => 497189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757641 [patent_doc_number] => 05754757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Efficient schemes for constructing reliable computing nodes in distributed systems' [patent_app_type] => 1 [patent_app_number] => 8/432184 [patent_app_country] => US [patent_app_date] => 1995-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5731 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754757.pdf [firstpage_image] =>[orig_patent_app_number] => 432184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526139 [patent_doc_number] => 05513319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Watchdog timer for computer system reset' [patent_app_type] => 1 [patent_app_number] => 8/488708 [patent_app_country] => US [patent_app_date] => 1995-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4138 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513319.pdf [firstpage_image] =>[orig_patent_app_number] => 488708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3639658 [patent_doc_number] => 05621885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'System and method for providing a fault tolerant computer program runtime support environment' [patent_app_type] => 1 [patent_app_number] => 8/475195 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621885.pdf [firstpage_image] =>[orig_patent_app_number] => 475195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3743341 [patent_doc_number] => 05666480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Fault-tolerant hierarchical bus system and method of operating same' [patent_app_type] => 1 [patent_app_number] => 8/484063 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 10455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666480.pdf [firstpage_image] =>[orig_patent_app_number] => 484063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3848860 [patent_doc_number] => 05761413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Fault containment system for multiprocessor with shared memory' [patent_app_type] => 1 [patent_app_number] => 8/462759 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9315 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761413.pdf [firstpage_image] =>[orig_patent_app_number] => 462759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705060 [patent_doc_number] => 05680404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Cycling error count for link maintenance' [patent_app_type] => 1 [patent_app_number] => 8/460733 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2253 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680404.pdf [firstpage_image] =>[orig_patent_app_number] => 460733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3902041 [patent_doc_number] => 05724504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Method for measuring architectural test coverage for design verification and building conformal test' [patent_app_type] => 1 [patent_app_number] => 8/457903 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4798 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724504.pdf [firstpage_image] =>[orig_patent_app_number] => 457903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118579 [patent_doc_number] => 06023561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'System for processing traceable cache trace information' [patent_app_type] => 1 [patent_app_number] => 8/456884 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5038 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023561.pdf [firstpage_image] =>[orig_patent_app_number] => 456884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3563775 [patent_doc_number] => 05572662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Data processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/455723 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12243 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572662.pdf [firstpage_image] =>[orig_patent_app_number] => 455723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3611896 [patent_doc_number] => 05559957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'File system for a data storage device having a power fail recovery mechanism for write/replace operations' [patent_app_type] => 1 [patent_app_number] => 8/455926 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5351 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559957.pdf [firstpage_image] =>[orig_patent_app_number] => 455926 [rel_patent_id] =>[rel_patent_doc_number] =>)