Search

Albert Decady

Supervisory Patent Examiner (ID: 19101, Phone: (571)272-3819 , Office: P/2112 )

Most Active Art Unit
2413
Art Unit(s)
2112, 2785, 2133, 2121, 2413, 2784, 2313
Total Applications
532
Issued Applications
390
Pending Applications
30
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3418674 [patent_doc_number] => 05461566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Method for minimalizing structural resonance on vehicle acceleration data' [patent_app_type] => 1 [patent_app_number] => 8/187877 [patent_app_country] => US [patent_app_date] => 1994-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2152 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461566.pdf [firstpage_image] =>[orig_patent_app_number] => 187877 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/187877
Method for minimalizing structural resonance on vehicle acceleration data Jan 26, 1994 Issued
Array ( [id] => 3562013 [patent_doc_number] => 05548720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Fault supervision method for transmission apparatus' [patent_app_type] => 1 [patent_app_number] => 8/182189 [patent_app_country] => US [patent_app_date] => 1994-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4455 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548720.pdf [firstpage_image] =>[orig_patent_app_number] => 182189 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/182189
Fault supervision method for transmission apparatus Jan 18, 1994 Issued
Array ( [id] => 3474373 [patent_doc_number] => 05469564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Data storage device with enhanced data security' [patent_app_type] => 1 [patent_app_number] => 8/181077 [patent_app_country] => US [patent_app_date] => 1994-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2120 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469564.pdf [firstpage_image] =>[orig_patent_app_number] => 181077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/181077
Data storage device with enhanced data security Jan 12, 1994 Issued
Array ( [id] => 3563894 [patent_doc_number] => 05572670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Bi-directional translator for diagnostic sensor data' [patent_app_type] => 1 [patent_app_number] => 8/179583 [patent_app_country] => US [patent_app_date] => 1994-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7659 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572670.pdf [firstpage_image] =>[orig_patent_app_number] => 179583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/179583
Bi-directional translator for diagnostic sensor data Jan 9, 1994 Issued
Array ( [id] => 3533993 [patent_doc_number] => 05530948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'System and method for command queuing on raid levels 4 and 5 parity drives' [patent_app_type] => 1 [patent_app_number] => 8/175710 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4788 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530948.pdf [firstpage_image] =>[orig_patent_app_number] => 175710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/175710
System and method for command queuing on raid levels 4 and 5 parity drives Dec 29, 1993 Issued
Array ( [id] => 3441011 [patent_doc_number] => 05463762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'I/O subsystem with header and error detection code generation and checking' [patent_app_type] => 1 [patent_app_number] => 8/176547 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463762.pdf [firstpage_image] =>[orig_patent_app_number] => 176547 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/176547
I/O subsystem with header and error detection code generation and checking Dec 29, 1993 Issued
Array ( [id] => 3601103 [patent_doc_number] => 05586126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Sample amplitude error detection and correction apparatus and method for use with a low information content signal' [patent_app_type] => 1 [patent_app_number] => 8/175733 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6767 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586126.pdf [firstpage_image] =>[orig_patent_app_number] => 175733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/175733
Sample amplitude error detection and correction apparatus and method for use with a low information content signal Dec 29, 1993 Issued
Array ( [id] => 3572890 [patent_doc_number] => 05526311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Method and circuitry for enabling and permanently disabling test mode access in a flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/175599 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8807 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526311.pdf [firstpage_image] =>[orig_patent_app_number] => 175599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/175599
Method and circuitry for enabling and permanently disabling test mode access in a flash memory device Dec 29, 1993 Issued
Array ( [id] => 3429229 [patent_doc_number] => 05479420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Clock fault monitoring circuit' [patent_app_type] => 1 [patent_app_number] => 8/173177 [patent_app_country] => US [patent_app_date] => 1993-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1861 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479420.pdf [firstpage_image] =>[orig_patent_app_number] => 173177 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173177
Clock fault monitoring circuit Dec 27, 1993 Issued
Array ( [id] => 3133181 [patent_doc_number] => 05450578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Method and apparatus for automatically routing around faults within an interconnect system' [patent_app_type] => 1 [patent_app_number] => 8/172647 [patent_app_country] => US [patent_app_date] => 1993-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10158 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450578.pdf [firstpage_image] =>[orig_patent_app_number] => 172647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172647
Method and apparatus for automatically routing around faults within an interconnect system Dec 22, 1993 Issued
Array ( [id] => 3531054 [patent_doc_number] => 05490148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Bit error rate estimator' [patent_app_type] => 1 [patent_app_number] => 8/166849 [patent_app_country] => US [patent_app_date] => 1993-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2081 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490148.pdf [firstpage_image] =>[orig_patent_app_number] => 166849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166849
Bit error rate estimator Dec 14, 1993 Issued
Array ( [id] => 3505113 [patent_doc_number] => 05537538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Debug mode for a superscalar RISC processor' [patent_app_type] => 1 [patent_app_number] => 8/166969 [patent_app_country] => US [patent_app_date] => 1993-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4538 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537538.pdf [firstpage_image] =>[orig_patent_app_number] => 166969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166969
Debug mode for a superscalar RISC processor Dec 14, 1993 Issued
08/148138 RECOVERY BOOT PROCESS Nov 2, 1993 Abandoned
Array ( [id] => 3432092 [patent_doc_number] => 05479610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'System interface fault isolator test set' [patent_app_type] => 1 [patent_app_number] => 8/144318 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3111 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479610.pdf [firstpage_image] =>[orig_patent_app_number] => 144318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/144318
System interface fault isolator test set Oct 31, 1993 Issued
Array ( [id] => 3492198 [patent_doc_number] => 05406566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit write-in test data signal stored in serial-input shift register' [patent_app_type] => 1 [patent_app_number] => 8/139717 [patent_app_country] => US [patent_app_date] => 1993-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4888 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406566.pdf [firstpage_image] =>[orig_patent_app_number] => 139717 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/139717
Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit write-in test data signal stored in serial-input shift register Oct 21, 1993 Issued
Array ( [id] => 3568895 [patent_doc_number] => 05502811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'System and method for striping data to magnetic tape units' [patent_app_type] => 1 [patent_app_number] => 8/129228 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502811.pdf [firstpage_image] =>[orig_patent_app_number] => 129228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/129228
System and method for striping data to magnetic tape units Sep 28, 1993 Issued
08/119347 ELECTRONIC APPARATUS Sep 8, 1993 Abandoned
Array ( [id] => 3505204 [patent_doc_number] => 05537544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Portable computer system having password control means for holding one or more passwords such that the passwords are unreadable by direct access from a main processor' [patent_app_type] => 1 [patent_app_number] => 8/106922 [patent_app_country] => US [patent_app_date] => 1993-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 17884 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537544.pdf [firstpage_image] =>[orig_patent_app_number] => 106922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/106922
Portable computer system having password control means for holding one or more passwords such that the passwords are unreadable by direct access from a main processor Aug 15, 1993 Issued
08/106158 METHOD OF TESTING INTERCONNECTIONS BETWEEN INTEGRATED CIRCUITS IN A CIRCUIT Aug 12, 1993 Abandoned
Array ( [id] => 3474359 [patent_doc_number] => 05469563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Method and control apparatus for self diagnosis' [patent_app_type] => 1 [patent_app_number] => 8/101198 [patent_app_country] => US [patent_app_date] => 1993-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469563.pdf [firstpage_image] =>[orig_patent_app_number] => 101198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/101198
Method and control apparatus for self diagnosis Aug 2, 1993 Issued
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