| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Fail-safe event driven transaction processing system and method'
[patent_app_type] => 1
[patent_app_number] => 8/741149
[patent_app_country] => US
[patent_app_date] => 1996-10-29
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Array
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[patent_doc_number] => 05784550
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Method for enhanced functional testing of a processor using dynamic trap handlers'
[patent_app_type] => 1
[patent_app_number] => 8/739244
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[firstpage_image] =>[orig_patent_app_number] => 739244
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739244 | Method for enhanced functional testing of a processor using dynamic trap handlers | Oct 28, 1996 | Issued |
Array
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[id] => 4017543
[patent_doc_number] => 05859964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes'
[patent_app_type] => 1
[patent_app_number] => 8/736919
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[firstpage_image] =>[orig_patent_app_number] => 736919
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Array
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[id] => 3849020
[patent_doc_number] => 05815654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Method for determining software reliability'
[patent_app_type] => 1
[patent_app_number] => 8/732624
[patent_app_country] => US
[patent_app_date] => 1996-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/815/05815654.pdf
[firstpage_image] =>[orig_patent_app_number] => 732624
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732624 | Method for determining software reliability | Oct 15, 1996 | Issued |
| 08/729095 | PROCESS CONTROL INTERFACE SYSTEM HAVING TRIPLY REDUNDANT REMOTE FIELD UNITS | Oct 10, 1996 | Abandoned |
Array
(
[id] => 4007687
[patent_doc_number] => 05892898
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[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Error management system for supporting the identification and logging of error messages'
[patent_app_type] => 1
[patent_app_number] => 8/720929
[patent_app_country] => US
[patent_app_date] => 1996-10-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/720929 | Error management system for supporting the identification and logging of error messages | Oct 3, 1996 | Issued |
Array
(
[id] => 3757724
[patent_doc_number] => 05754763
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Software auditing mechanism for a distributed computer enterprise environment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/724659 | Software auditing mechanism for a distributed computer enterprise environment | Sep 30, 1996 | Issued |
Array
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[id] => 3894104
[patent_doc_number] => 05826012
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[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Boot-time anti-virus and maintenance facility'
[patent_app_type] => 1
[patent_app_number] => 8/714938
[patent_app_country] => US
[patent_app_date] => 1996-09-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/826/05826012.pdf
[firstpage_image] =>[orig_patent_app_number] => 714938
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/714938 | Boot-time anti-virus and maintenance facility | Sep 16, 1996 | Issued |
Array
(
[id] => 3811258
[patent_doc_number] => 05781721
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Method and apparatus for testing cache RAM residing on a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/714515
[patent_app_country] => US
[patent_app_date] => 1996-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/781/05781721.pdf
[firstpage_image] =>[orig_patent_app_number] => 714515
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/714515 | Method and apparatus for testing cache RAM residing on a microprocessor | Sep 15, 1996 | Issued |
Array
(
[id] => 3796088
[patent_doc_number] => 05819025
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[patent_issue_date] => 1998-10-06
[patent_title] => 'Method of testing interconnections between integrated circuits in a circuit'
[patent_app_type] => 1
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[pdf_file] => patents/05/819/05819025.pdf
[firstpage_image] =>[orig_patent_app_number] => 714619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/714619 | Method of testing interconnections between integrated circuits in a circuit | Sep 15, 1996 | Issued |
Array
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[id] => 4041893
[patent_doc_number] => 05903718
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[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Remote program monitor method and system using a system-under-test microcontroller for self-debug'
[patent_app_type] => 1
[patent_app_number] => 8/714729
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Array
(
[id] => 4030563
[patent_doc_number] => 05881224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle'
[patent_app_type] => 1
[patent_app_number] => 8/711574
[patent_app_country] => US
[patent_app_date] => 1996-09-10
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 711574
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711574 | Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle | Sep 9, 1996 | Issued |
| 08/682504 | COMPUTER SECURITY SYSTEM | Sep 8, 1996 | Abandoned |
Array
(
[id] => 3942926
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[patent_kind] => NA
[patent_issue_date] => 1999-03-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705978 | Disk system and factory automation controller and method therefor | Aug 29, 1996 | Issued |
Array
(
[id] => 4069741
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[patent_issue_date] => 1999-01-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705478 | Auditing login activity in a distributed computing environment | Aug 19, 1996 | Issued |
Array
(
[id] => 3857193
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Boundary scan test method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/689876
[patent_app_country] => US
[patent_app_date] => 1996-08-15
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[firstpage_image] =>[orig_patent_app_number] => 689876
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/689876 | Boundary scan test method and apparatus | Aug 14, 1996 | Issued |
| 08/693459 | METHOD AND APPARATUS FOR AUTOMATICALLY SCRUBBING ECC ERRORS IN MEMORY VIA HARDWARE | Aug 6, 1996 | Abandoned |
| 08/692611 | PROCESSOR THAT REDIRECTS AN INSTRUCTION FETCH PIPELINE IMMEDIATELY UPON DETECTION OF A MISPREDICTED BRANCH WHILE COMMITTING PRIOR INSTRUCTIONS TO AN ARCHITECTURAL STATE | Aug 5, 1996 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/686443 | System and method for managing faults in a distributed system | Jul 24, 1996 | Issued |
Array
(
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[patent_kind] => NA
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