Search

Albert H. Cutler

Examiner (ID: 15194, Phone: (571)270-1460 , Office: P/2661 )

Most Active Art Unit
2661
Art Unit(s)
2622, 2637, 2661, 2696
Total Applications
1227
Issued Applications
947
Pending Applications
84
Abandoned Applications
241

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14920585 [patent_doc_number] => 10431620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor device and electronic appliance [patent_app_type] => utility [patent_app_number] => 15/784699 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784699
Semiconductor device and electronic appliance Oct 15, 2017 Issued
Array ( [id] => 12181683 [patent_doc_number] => 20180040619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 15/729002 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729002
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Oct 9, 2017 Issued
Array ( [id] => 14094371 [patent_doc_number] => 10243100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Semiconductor layer including compositional inhomogeneities [patent_app_type] => utility [patent_app_number] => 15/687606 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 60 [patent_no_of_words] => 15087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687606
Semiconductor layer including compositional inhomogeneities Aug 27, 2017 Issued
Array ( [id] => 13695397 [patent_doc_number] => 20170358653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => Semiconductor Structure With Enlarged Gate Electrode Structure And Method For Forming The Same [patent_app_type] => utility [patent_app_number] => 15/687308 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687308
Semiconductor structure with enlarged gate electrode structure and method for forming the same Aug 24, 2017 Issued
Array ( [id] => 13071007 [patent_doc_number] => 10056288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Semiconductor device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/672272 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1782 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672272
Semiconductor device and fabrication method thereof Aug 7, 2017 Issued
Array ( [id] => 12823447 [patent_doc_number] => 20180166321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR DEVICE WITH REDUCED TRENCH LOADING EFFECT [patent_app_type] => utility [patent_app_number] => 15/672123 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672123
Semiconductor device with reduced trench loading effect Aug 7, 2017 Issued
Array ( [id] => 13909031 [patent_doc_number] => 20190043720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MANUFACTURING SYSTEM AND METHOD FOR FORMING A CLEAN INTERFACE BETWEEN A FUNCTIONAL LAYER AND A TWO-DIMENSIONAL LAYEYED SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 15/665486 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665486
Manufacturing system and method for forming a clean interface between a functional layer and a two-dimensional layeyed semiconductor Jul 31, 2017 Issued
Array ( [id] => 16495685 [patent_doc_number] => 10861733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/664367 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 90 [patent_no_of_words] => 35109 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15664367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/664367
Manufacturing method of semiconductor device Jul 30, 2017 Issued
Array ( [id] => 13057293 [patent_doc_number] => 10050045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => SRAM cell with balanced write port [patent_app_type] => utility [patent_app_number] => 15/625490 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625490
SRAM cell with balanced write port Jun 15, 2017 Issued
Array ( [id] => 12250243 [patent_doc_number] => 09923027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Structure and method for memory cell array' [patent_app_type] => utility [patent_app_number] => 15/624865 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624865
Structure and method for memory cell array Jun 15, 2017 Issued
Array ( [id] => 13629801 [patent_doc_number] => 20180366453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => METHOD AND APPARATUS FOR REDUCING CAPACITANCE OF INPUT/OUTPUT PINS OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/625350 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625350 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625350
Method and apparatus for reducing capacitance of input/output pins of memory device Jun 15, 2017 Issued
Array ( [id] => 13724615 [patent_doc_number] => 20170373263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Organic/Inorganic Hybrid Electroluminescent Device with Two-Dimensional Material Emitting Layer [patent_app_type] => utility [patent_app_number] => 15/625310 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625310
Organic/Inorganic Hybrid Electroluminescent Device with Two-Dimensional Material Emitting Layer Jun 15, 2017 Abandoned
Array ( [id] => 14397823 [patent_doc_number] => 10312203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Structure and formation method of chip package with antenna element [patent_app_type] => utility [patent_app_number] => 15/625678 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 7128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625678
Structure and formation method of chip package with antenna element Jun 15, 2017 Issued
Array ( [id] => 13030755 [patent_doc_number] => 10038001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => Hybrid electrically erasable programmable read-only memory (EEPROM) systems and methods for forming [patent_app_type] => utility [patent_app_number] => 15/624886 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624886
Hybrid electrically erasable programmable read-only memory (EEPROM) systems and methods for forming Jun 15, 2017 Issued
Array ( [id] => 14738813 [patent_doc_number] => 10388818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Semiconductor detector [patent_app_type] => utility [patent_app_number] => 15/625473 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3735 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625473
Semiconductor detector Jun 15, 2017 Issued
Array ( [id] => 13057141 [patent_doc_number] => 10049969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Integrated circuit [patent_app_type] => utility [patent_app_number] => 15/624875 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7000 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624875 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624875
Integrated circuit Jun 15, 2017 Issued
Array ( [id] => 12478170 [patent_doc_number] => 09991312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-05 [patent_title] => Electroluminescence display apparatus and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/623863 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7414 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623863
Electroluminescence display apparatus and manufacturing method thereof Jun 14, 2017 Issued
Array ( [id] => 16594096 [patent_doc_number] => 10903373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Chip diode and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/488145 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 82 [patent_no_of_words] => 30884 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488145
Chip diode and method for manufacturing same Apr 13, 2017 Issued
Array ( [id] => 16001133 [patent_doc_number] => 20200176437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHOD AND DEVICE FOR BONDING OF CHIPS [patent_app_type] => utility [patent_app_number] => 16/483077 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/483077
Method and device for bonding of chips Mar 1, 2017 Issued
Array ( [id] => 11694629 [patent_doc_number] => 20170170346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'NECKLACES OF SILICON NANOWIRES' [patent_app_type] => utility [patent_app_number] => 15/441744 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15441744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/441744
Necklaces of silicon nanowires Feb 23, 2017 Issued
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