Search

Albert H. Cutler

Examiner (ID: 15194, Phone: (571)270-1460 , Office: P/2661 )

Most Active Art Unit
2661
Art Unit(s)
2622, 2637, 2661, 2696
Total Applications
1227
Issued Applications
947
Pending Applications
84
Abandoned Applications
241

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17196158 [patent_doc_number] => 11164925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/366066 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10633 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/366066
Display device and manufacturing method thereof Mar 26, 2019 Issued
Array ( [id] => 17339567 [patent_doc_number] => 20220005898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/469651 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16469651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/469651
OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF Mar 18, 2019 Abandoned
Array ( [id] => 14542875 [patent_doc_number] => 20190207059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Semiconductor Layer Including Compositional Inhomogeneities [patent_app_type] => utility [patent_app_number] => 16/299362 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299362
Semiconductor layer including compositional inhomogeneities Mar 11, 2019 Issued
Array ( [id] => 19244582 [patent_doc_number] => 12015037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Imaging device and method of manufacturing imaging device [patent_app_type] => utility [patent_app_number] => 17/044994 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17044994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/044994
Imaging device and method of manufacturing imaging device Jan 16, 2019 Issued
Array ( [id] => 14316875 [patent_doc_number] => 20190148141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/246805 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246805
Semiconductor device and method for forming the same Jan 13, 2019 Issued
Array ( [id] => 16896472 [patent_doc_number] => 11038035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor structure with enlarged gate electrode structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/197258 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6340 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197258
Semiconductor structure with enlarged gate electrode structure and method for forming the same Nov 19, 2018 Issued
Array ( [id] => 16759895 [patent_doc_number] => 10978452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry [patent_app_type] => utility [patent_app_number] => 16/193905 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 54 [patent_no_of_words] => 6806 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193905
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry Nov 15, 2018 Issued
Array ( [id] => 14024723 [patent_doc_number] => 20190074355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => ELONGATED SEMICONDUCTOR STRUCTURE PLANARIZATION [patent_app_type] => utility [patent_app_number] => 16/179645 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179645
Elongated semiconductor structure planarization Nov 1, 2018 Issued
Array ( [id] => 16308746 [patent_doc_number] => 10777556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/149125 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2888 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149125
Semiconductor device and method for fabricating the same Sep 30, 2018 Issued
Array ( [id] => 16432958 [patent_doc_number] => 10833055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Semiconductor device and optical coupling device [patent_app_type] => utility [patent_app_number] => 16/132702 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4549 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132702
Semiconductor device and optical coupling device Sep 16, 2018 Issued
Array ( [id] => 15568605 [patent_doc_number] => 20200068714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE WITH EMBEDDED FUNCTIONALITIES AND RELATED MULTILAYER STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/113388 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113388
Method for manufacturing a multilayer structure with embedded functionalities and related multilayer structure Aug 26, 2018 Issued
Array ( [id] => 13629671 [patent_doc_number] => 20180366388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/110389 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/110389
Circuit module and manufacturing method thereof Aug 22, 2018 Issued
Array ( [id] => 16339283 [patent_doc_number] => 10790252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/050678 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 696 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050678
Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices Jul 30, 2018 Issued
Array ( [id] => 15315673 [patent_doc_number] => 10522553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => SRAM cell with balanced write port [patent_app_type] => utility [patent_app_number] => 16/047586 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047586
SRAM cell with balanced write port Jul 26, 2018 Issued
Array ( [id] => 15351945 [patent_doc_number] => 20200013864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/483396 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/483396
Gate structure of semiconductor device and manufacturing method therefor Jul 2, 2018 Issued
Array ( [id] => 15234325 [patent_doc_number] => 10504892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/018616 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018616
Semiconductor device Jun 25, 2018 Issued
Array ( [id] => 15785569 [patent_doc_number] => 10626495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Bottom-up growth of silicon oxide and silicon nitride using sequential deposition-etch-treat processing [patent_app_type] => utility [patent_app_number] => 16/001258 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001258
Bottom-up growth of silicon oxide and silicon nitride using sequential deposition-etch-treat processing Jun 5, 2018 Issued
Array ( [id] => 17002526 [patent_doc_number] => 11081348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Selective deposition of silicon using deposition-treat-etch process [patent_app_type] => utility [patent_app_number] => 16/001251 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001251
Selective deposition of silicon using deposition-treat-etch process Jun 5, 2018 Issued
Array ( [id] => 13629919 [patent_doc_number] => 20180366512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/001144 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001144 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001144
Method of manufacturing semiconductor device Jun 5, 2018 Issued
Array ( [id] => 17002526 [patent_doc_number] => 11081348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Selective deposition of silicon using deposition-treat-etch process [patent_app_type] => utility [patent_app_number] => 16/001251 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001251
Selective deposition of silicon using deposition-treat-etch process Jun 5, 2018 Issued
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