Search

Albert Kang Wong

Examiner (ID: 14906, Phone: (571)272-3057 , Office: P/3649 )

Most Active Art Unit
2612
Art Unit(s)
2612, 3649, 2689, 2617, 2735, 2635, 2683, 2685
Total Applications
1756
Issued Applications
1254
Pending Applications
128
Abandoned Applications
379

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20096896 [patent_doc_number] => 20250226832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR ANALOG COMPUTING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/738844 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738844
ELECTRONIC DEVICE AND METHOD FOR ANALOG COMPUTING CIRCUIT Jun 9, 2024 Pending
Array ( [id] => 19804868 [patent_doc_number] => 20250070793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => DIGITAL-TO-ANALOG CONVERTER [patent_app_type] => utility [patent_app_number] => 18/679005 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679005 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679005
DIGITAL-TO-ANALOG CONVERTER May 29, 2024 Pending
Array ( [id] => 20395485 [patent_doc_number] => 20250370960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => ADJUSTING FILES FOR HUMAN READABLE PRIME NUMBER COMPRESSION (HRPNC) ACCELERATION [patent_app_type] => utility [patent_app_number] => 18/678081 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678081 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678081
ADJUSTING FILES FOR HUMAN READABLE PRIME NUMBER COMPRESSION (HRPNC) ACCELERATION May 29, 2024 Pending
Array ( [id] => 20625201 [patent_doc_number] => 12592717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Integrator circuit [patent_app_type] => utility [patent_app_number] => 18/674377 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674377
INTEGRATOR CIRCUIT May 23, 2024 Pending
Array ( [id] => 20382507 [patent_doc_number] => 20250365000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => HIGH INPUT IMPEDANCE LOW POWER ADC [patent_app_type] => utility [patent_app_number] => 18/674266 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674266
HIGH INPUT IMPEDANCE LOW POWER ADC May 23, 2024 Pending
Array ( [id] => 20382515 [patent_doc_number] => 20250365008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => METHODS OF CONSTRUCTING AND USING LOW-POWER QDE-ZIPPER CODES, AND SYSTEMS, APPARATUSES, METHODS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE DEVICES EMPLOYING SAME [patent_app_type] => utility [patent_app_number] => 18/671663 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671663
METHODS OF CONSTRUCTING AND USING LOW-POWER QDE-ZIPPER CODES, AND SYSTEMS, APPARATUSES, METHODS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE DEVICES EMPLOYING SAME May 21, 2024 Pending
Array ( [id] => 20000600 [patent_doc_number] => 20250138822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SYSTEMS AND METHODS FOR INSTRUCTION-SET AWARE ARITHMETIC CODING FOR EFFICIENT CODE COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/666540 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666540
SYSTEMS AND METHODS FOR INSTRUCTION-SET AWARE ARITHMETIC CODING FOR EFFICIENT CODE COMPRESSION May 15, 2024 Pending
Array ( [id] => 20353440 [patent_doc_number] => 20250350292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => DIGITAL-TO-ANALOG CONVERTER CALIBRATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/658789 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658789
DIGITAL-TO-ANALOG CONVERTER CALIBRATION SYSTEM May 7, 2024 Pending
Array ( [id] => 20054579 [patent_doc_number] => 20250192801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/650118 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650118
DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS Apr 29, 2024 Pending
Array ( [id] => 20325346 [patent_doc_number] => 20250337434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MACHINE LEARNING ENHANCED RESOLVER SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/646432 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646432
MACHINE LEARNING ENHANCED RESOLVER SYSTEMS Apr 24, 2024 Pending
Array ( [id] => 20530752 [patent_doc_number] => 12549196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Systems and methods for dynamically generating and mapping unicode for cross-distributed network data transmissions [patent_app_type] => utility [patent_app_number] => 18/643252 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643252
Systems and methods for dynamically generating and mapping unicode for cross-distributed network data transmissions Apr 22, 2024 Issued
Array ( [id] => 19547322 [patent_doc_number] => 20240364358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SIGMA-DELTA MODULATOR AND METHOD FOR OPERATING A SIGMA-DELTA MODULATOR [patent_app_type] => utility [patent_app_number] => 18/641888 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641888 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641888
SIGMA-DELTA MODULATOR AND METHOD FOR OPERATING A SIGMA-DELTA MODULATOR Apr 21, 2024 Pending
Array ( [id] => 19821926 [patent_doc_number] => 20250080133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => OPTIMIZATIONS FOR RESOLVER-TO-DIGITAL CONVERTERS [patent_app_type] => utility [patent_app_number] => 18/637102 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637102
OPTIMIZATIONS FOR RESOLVER-TO-DIGITAL CONVERTERS Apr 15, 2024 Pending
Array ( [id] => 20298410 [patent_doc_number] => 20250323653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => SELF-CALIBRATING DELAY LINE FLASH ADC AND TRACKING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/636667 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636667
SELF-CALIBRATING DELAY LINE FLASH ADC AND TRACKING CIRCUITRY Apr 15, 2024 Pending
Array ( [id] => 20404810 [patent_doc_number] => 12494794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Analog-to-digital converter (ADC) having selective comparator offset error tracking and related corrections [patent_app_type] => utility [patent_app_number] => 18/629230 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629230
Analog-to-digital converter (ADC) having selective comparator offset error tracking and related corrections Apr 7, 2024 Issued
Array ( [id] => 20495655 [patent_doc_number] => 12537537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Analog-to-digital conversion apparatus and method having dynamic gain compensation mechanism [patent_app_type] => utility [patent_app_number] => 18/613185 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613185
Analog-to-digital conversion apparatus and method having dynamic gain compensation mechanism Mar 21, 2024 Issued
Array ( [id] => 20251801 [patent_doc_number] => 20250300670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => BUS CONTROL FOR DC/DC CONVERTERS [patent_app_type] => utility [patent_app_number] => 18/609686 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609686
Bus control for DC/DC converters Mar 18, 2024 Issued
Array ( [id] => 19286717 [patent_doc_number] => 20240223197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Method for Compensating Electrical Device Variabilities in Configurable-Output Circuit and Device [patent_app_type] => utility [patent_app_number] => 18/601429 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601429
Method for Compensating Electrical Device Variabilities in Configurable-Output Circuit and Device Mar 10, 2024 Pending
Array ( [id] => 20551948 [patent_doc_number] => 12562751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Relating to quantum computing [patent_app_type] => utility [patent_app_number] => 18/599045 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599045
Relating to quantum computing Mar 6, 2024 Issued
Array ( [id] => 20581781 [patent_doc_number] => 12574039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Real-equivalent-time oscilloscope and wideband real-time spectrum analyzer [patent_app_type] => utility [patent_app_number] => 18/591468 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 3233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591468
Real-equivalent-time oscilloscope and wideband real-time spectrum analyzer Feb 28, 2024 Issued
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