Search

Albert Kir

Examiner (ID: 4004, Phone: (571)272-6245 , Office: P/2489 )

Most Active Art Unit
2485
Art Unit(s)
2489, 2485
Total Applications
564
Issued Applications
336
Pending Applications
83
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17070663 [patent_doc_number] => 20210272880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING COMPOSITE MOLDING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/016115 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/016115
Semiconductor package including composite molding structure Sep 8, 2020 Issued
Array ( [id] => 16692176 [patent_doc_number] => 20210074655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SECURED FLOATING GATE TRANSISTOR AND METHOD FOR SECURING FLOATING GATE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/011190 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011190
SECURED FLOATING GATE TRANSISTOR AND METHOD FOR SECURING FLOATING GATE TRANSISTORS Sep 2, 2020 Abandoned
Array ( [id] => 18913046 [patent_doc_number] => 11876033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor device including resin case having groove at corner thereof [patent_app_type] => utility [patent_app_number] => 17/005594 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4380 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005594
Semiconductor device including resin case having groove at corner thereof Aug 27, 2020 Issued
Array ( [id] => 16556983 [patent_doc_number] => 20210002131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHOD FOR MANUFACTURING MICROMECHANICAL STRUCTURES IN A DEVICE WAFER [patent_app_type] => utility [patent_app_number] => 17/003703 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003703
Method for manufacturing micromechanical structures in a device wafer Aug 25, 2020 Issued
Array ( [id] => 19584221 [patent_doc_number] => 12150371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Organic light emitting diode display substrate, preparation method and repair method therefor and organic light emitting diode display apparatus [patent_app_type] => utility [patent_app_number] => 17/288927 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 11644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17288927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/288927
Organic light emitting diode display substrate, preparation method and repair method therefor and organic light emitting diode display apparatus Aug 19, 2020 Issued
Array ( [id] => 18277076 [patent_doc_number] => 11616024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Storage device including semiconductor chips sealed with resin on metal plate [patent_app_type] => utility [patent_app_number] => 16/988532 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2288 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16988532 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/988532
Storage device including semiconductor chips sealed with resin on metal plate Aug 6, 2020 Issued
Array ( [id] => 17284203 [patent_doc_number] => 11201247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => LTPS type TFT and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 16/942800 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5709 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942800
LTPS type TFT and method for manufacturing same Jul 29, 2020 Issued
Array ( [id] => 16617241 [patent_doc_number] => 20210035894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => LEAD FRAME FOR A PACKAGE FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/940815 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940815
Lead frame for a package for a semiconductor device, semiconductor device and process for manufacturing a semiconductor device Jul 27, 2020 Issued
Array ( [id] => 17787790 [patent_doc_number] => 11410926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => E-fuse enhancement by underlayer layout design [patent_app_type] => utility [patent_app_number] => 16/938450 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938450
E-fuse enhancement by underlayer layout design Jul 23, 2020 Issued
Array ( [id] => 16440411 [patent_doc_number] => 20200357738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => STACKED VIA STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/936436 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936436 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936436
Stacked via structure Jul 22, 2020 Issued
Array ( [id] => 17795910 [patent_doc_number] => 20220255002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => PROCESS FOR PRODUCING INVERTED POLYMER PHOTOVOLTAIC CELLS [patent_app_type] => utility [patent_app_number] => 17/626065 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626065
PROCESS FOR PRODUCING INVERTED POLYMER PHOTOVOLTAIC CELLS Jul 7, 2020 Abandoned
Array ( [id] => 17347127 [patent_doc_number] => 20220013458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => VERTICAL ELECTRICAL FUSE DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/922628 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922628
Vertical electrical fuse device including fuse link disposed over semiconductor base and method for forming the same Jul 6, 2020 Issued
Array ( [id] => 16904799 [patent_doc_number] => 20210183715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/908378 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908378
Semiconductor module and semiconductor device Jun 21, 2020 Issued
Array ( [id] => 20375208 [patent_doc_number] => 12482652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Method for forming integrated circuit structures [patent_app_type] => utility [patent_app_number] => 17/624174 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6928 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17624174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/624174
Method for forming integrated circuit structures Jun 18, 2020 Issued
Array ( [id] => 17956552 [patent_doc_number] => 11482667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Nonvolatile memory device having a resistance change layer and a plurality of electrode pattern layers [patent_app_type] => utility [patent_app_number] => 16/904825 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904825
Nonvolatile memory device having a resistance change layer and a plurality of electrode pattern layers Jun 17, 2020 Issued
Array ( [id] => 18533220 [patent_doc_number] => 20230238296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/918907 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/918907
Semiconductor device including stop islands and method for manufacturing semiconductor device May 24, 2020 Issued
Array ( [id] => 16257446 [patent_doc_number] => 20200266821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS [patent_app_type] => utility [patent_app_number] => 15/929520 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929520
Multiple via structure for high performance standard cells May 6, 2020 Issued
Array ( [id] => 18402168 [patent_doc_number] => 11664316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Semiconductor devices having penetration vias with portions having decreasing widths [patent_app_type] => utility [patent_app_number] => 16/849085 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6712 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849085
Semiconductor devices having penetration vias with portions having decreasing widths Apr 14, 2020 Issued
Array ( [id] => 17210785 [patent_doc_number] => 11171162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Display device having scan lines of different lengths [patent_app_type] => utility [patent_app_number] => 16/839121 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4999 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/839121
Display device having scan lines of different lengths Apr 2, 2020 Issued
Array ( [id] => 17668571 [patent_doc_number] => 11362276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => High thermal stability SiO [patent_app_type] => utility [patent_app_number] => 16/833349 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7353 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833349
High thermal stability SiO Mar 26, 2020 Issued
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