Albert Kir

Array ( [id] => 18387424 [patent_doc_number] => 11658219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/371301 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097389 [patent_doc_number] => 20220415730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR MODULE HAVING PROTRUSIONS AS FIXING STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/362088 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097389 [patent_doc_number] => 20220415730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR MODULE HAVING PROTRUSIONS AS FIXING STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/362088 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097389 [patent_doc_number] => 20220415730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR MODULE HAVING PROTRUSIONS AS FIXING STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/362088 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097389 [patent_doc_number] => 20220415730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR MODULE HAVING PROTRUSIONS AS FIXING STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/362088 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17347136 [patent_doc_number] => 20220013467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 17/358752 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097315 [patent_doc_number] => 20220415656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => BACKSIDE WAFER DOPANT ACTIVATION [patent_app_type] => utility [patent_app_number] => 17/358244 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18704635 [patent_doc_number] => 11791152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Residue removal during semiconductor device formation [patent_app_type] => utility [patent_app_number] => 17/344168 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2882 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115793 [patent_doc_number] => 20210296390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => PIXEL HAVING TWO SEMICONDUCTOR LAYERS, IMAGE SENSOR INCLUDING THE PIXEL, AND IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/340273 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19957380 [patent_doc_number] => 12327799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor device and method of forming multi-layer shielding structure with layers of ferromagnetic material, protective material, laminate material or conductive material over the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/317082 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 0 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17055793 [patent_doc_number] => 20210265227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => STRUCTURES FOR BONDING ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/315170 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18236001 [patent_doc_number] => 11600566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Integrated circuit e-fuse having an e-fuse element providing a diffusion barrier for underlying e-fuse terminals [patent_app_type] => utility [patent_app_number] => 17/233311 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7498 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18631857 [patent_doc_number] => 20230290762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => FLIP CHIP MICROLED AND CARTRIDGE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/918720 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17583008 [patent_doc_number] => 20220139863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INTEGRATED CIRCUIT CHIP HAVING BS-PDN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/228111 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16981177 [patent_doc_number] => 20210225414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => MRAM STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/224153 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16951903 [patent_doc_number] => 20210210595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/209242 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18883019 [patent_doc_number] => 20240006388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => DISPLAY MODULE [patent_app_type] => utility [patent_app_number] => 18/271781 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18271781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17855107 [patent_doc_number] => 20220285150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD FOR FORMING CONTACT SURFACE ON TOP OF MESA STRUCTURE FORMED ON SEMICONDUCTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/192233 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18859164 [patent_doc_number] => 11856774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor memory device that includes a semiconductor column that penetrates a plurality of conductive layers [patent_app_type] => utility [patent_app_number] => 17/181027 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 15330 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18277155 [patent_doc_number] => 11616105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Display device structure for reducing defects [patent_app_type] => utility [patent_app_number] => 17/179825 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179825 [rel_patent_id] =>[rel_patent_doc_number] =>)