| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3590689
[patent_doc_number] => 05491828
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect'
[patent_app_type] => 1
[patent_app_number] => 8/307399
[patent_app_country] => US
[patent_app_date] => 1994-09-16
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 307399
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307399 | Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect | Sep 15, 1994 | Issued |
| 08/307402 | INTEGRATED DATA PROCESSING SYSTEM INCLUDING CPU CORE AND PARALLEL, INDEPENDENTLY OPERATING DSP MODULE AND HAVING MULTIPLE OPERATING MODES | Sep 15, 1994 | Abandoned |
| 08/307406 | MECHANISM FOR HANDLING NON-MASKABLE INTERRUPT REQUESTS RECEIVED FROM DIFFERENT SOURCES | Sep 15, 1994 | Abandoned |
Array
(
[id] => 3660848
[patent_doc_number] => 05630151
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Data driven information processor generating multidimensional generation number identifying generation and additional attributes of data in data packet'
[patent_app_type] => 1
[patent_app_number] => 8/299098
[patent_app_country] => US
[patent_app_date] => 1994-09-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/630/05630151.pdf
[firstpage_image] =>[orig_patent_app_number] => 299098
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299098 | Data driven information processor generating multidimensional generation number identifying generation and additional attributes of data in data packet | Sep 1, 1994 | Issued |
| 08/299296 | AUTOMATIC INSTRUCTION STRING GENERATING METHOD AND DEVICE FOR VERIFYING OPERATIONS OF PIPELINE CONTROL MECHANISM OF A PROCESSOR | Aug 31, 1994 | Abandoned |
| 08/299146 | A CONFIGURATION SPACE ACCESS ENABLE/DISABLE MECHANISM FOR A HIERARCHICAL COMPUTER SYSTEM | Aug 30, 1994 | Abandoned |
Array
(
[id] => 3567031
[patent_doc_number] => 05519879
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Integrated circuit having CPU and DSP for executing vector lattice propagation instruction and updating values of vector Z in a single instruction cycle'
[patent_app_type] => 1
[patent_app_number] => 8/296642
[patent_app_country] => US
[patent_app_date] => 1994-08-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/519/05519879.pdf
[firstpage_image] =>[orig_patent_app_number] => 296642
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/296642 | Integrated circuit having CPU and DSP for executing vector lattice propagation instruction and updating values of vector Z in a single instruction cycle | Aug 25, 1994 | Issued |
Array
(
[id] => 3676108
[patent_doc_number] => 05625830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Reduced circuit, high performance, binary select encoder network'
[patent_app_type] => 1
[patent_app_number] => 8/289826
[patent_app_country] => US
[patent_app_date] => 1994-08-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/625/05625830.pdf
[firstpage_image] =>[orig_patent_app_number] => 289826
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/289826 | Reduced circuit, high performance, binary select encoder network | Aug 11, 1994 | Issued |
Array
(
[id] => 3636419
[patent_doc_number] => 05594912
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Digital signal processing device with optimized ALU circuit and logic block for controlling one of two registers based on the contents of the multiplication register'
[patent_app_type] => 1
[patent_app_number] => 8/287766
[patent_app_country] => US
[patent_app_date] => 1994-08-09
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[pdf_file] => patents/05/594/05594912.pdf
[firstpage_image] =>[orig_patent_app_number] => 287766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/287766 | Digital signal processing device with optimized ALU circuit and logic block for controlling one of two registers based on the contents of the multiplication register | Aug 8, 1994 | Issued |
Array
(
[id] => 3605607
[patent_doc_number] => 05522045
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement'
[patent_app_type] => 1
[patent_app_number] => 8/286799
[patent_app_country] => US
[patent_app_date] => 1994-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/522/05522045.pdf
[firstpage_image] =>[orig_patent_app_number] => 286799
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/286799 | Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement | Aug 3, 1994 | Issued |
| 08/283165 | DATA PROCESSING APPARATUS INCLUDING DISPLAY DEVICE HAVING MEMORY FUNCTION | Aug 2, 1994 | Abandoned |
Array
(
[id] => 3505225
[patent_doc_number] => 05537545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'System for controlling cooperations among a plurality of terminals connected to a network whereby each terminal can be switched from cooperative to individual operation mode'
[patent_app_type] => 1
[patent_app_number] => 8/278156
[patent_app_country] => US
[patent_app_date] => 1994-07-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/537/05537545.pdf
[firstpage_image] =>[orig_patent_app_number] => 278156
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/278156 | System for controlling cooperations among a plurality of terminals connected to a network whereby each terminal can be switched from cooperative to individual operation mode | Jul 20, 1994 | Issued |
Array
(
[id] => 3606228
[patent_doc_number] => 05522080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Centralized control SIMD processor having different priority levels set for each data transfer request type and successively repeating the servicing of data transfer request in a predetermined order'
[patent_app_type] => 1
[patent_app_number] => 8/277772
[patent_app_country] => US
[patent_app_date] => 1994-07-20
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[firstpage_image] =>[orig_patent_app_number] => 277772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/277772 | Centralized control SIMD processor having different priority levels set for each data transfer request type and successively repeating the servicing of data transfer request in a predetermined order | Jul 19, 1994 | Issued |
Array
(
[id] => 3627030
[patent_doc_number] => 05511219
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core'
[patent_app_type] => 1
[patent_app_number] => 8/274589
[patent_app_country] => US
[patent_app_date] => 1994-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
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[pdf_file] => patents/05/511/05511219.pdf
[firstpage_image] =>[orig_patent_app_number] => 274589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/274589 | Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core | Jul 12, 1994 | Issued |
| 08/273789 | POS SYSTEM | Jul 11, 1994 | Abandoned |
Array
(
[id] => 3676080
[patent_doc_number] => 05625828
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Parallel operating CPU core and DSP module for executing sequence of vector DSP code instructions to generate decoded constellation points in QAM/TCM modem application'
[patent_app_type] => 1
[patent_app_number] => 8/271204
[patent_app_country] => US
[patent_app_date] => 1994-07-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/625/05625828.pdf
[firstpage_image] =>[orig_patent_app_number] => 271204
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/271204 | Parallel operating CPU core and DSP module for executing sequence of vector DSP code instructions to generate decoded constellation points in QAM/TCM modem application | Jun 30, 1994 | Issued |
Array
(
[id] => 3589340
[patent_doc_number] => 05524254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Scheme for interlocking line card to an address recognition engine to support plurality of routing and bridging protocols by using network information look-up database'
[patent_app_type] => 1
[patent_app_number] => 8/269997
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[firstpage_image] =>[orig_patent_app_number] => 269997
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269997 | Scheme for interlocking line card to an address recognition engine to support plurality of routing and bridging protocols by using network information look-up database | Jun 30, 1994 | Issued |
Array
(
[id] => 3505690
[patent_doc_number] => 05537575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information'
[patent_app_type] => 1
[patent_app_number] => 8/268403
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268403 | System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information | Jun 29, 1994 | Issued |
Array
(
[id] => 3707766
[patent_doc_number] => 05596730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Interfaces for cross-connect system'
[patent_app_type] => 1
[patent_app_number] => 8/269065
[patent_app_country] => US
[patent_app_date] => 1994-06-30
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 269065
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269065 | Interfaces for cross-connect system | Jun 29, 1994 | Issued |
Array
(
[id] => 3503323
[patent_doc_number] => 05561784
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses'
[patent_app_type] => 1
[patent_app_number] => 8/268660
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268660 | Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses | Jun 28, 1994 | Issued |