| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1994-12-20
[patent_title] => 'Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories'
[patent_app_type] => 1
[patent_app_number] => 8/099117
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/099117 | Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories | Jul 28, 1993 | Issued |
| 08/089947 | METHOD AND APPARATUS FOR CONTROLLING THE EXECUTION OF HOST COMPUTER APPLICATION PROGRAMS THROUGH A SECOND COMPUTER | Jul 11, 1993 | Pending |
Array
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[id] => 3537812
[patent_doc_number] => 05504914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Multi-level instruction boosting method using plurality of ordinary registers forming plurality of conjugate register pairs that are shadow registers to each other with different only in MSB'
[patent_app_type] => 1
[patent_app_number] => 8/082130
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[firstpage_image] =>[orig_patent_app_number] => 082130
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/082130 | Multi-level instruction boosting method using plurality of ordinary registers forming plurality of conjugate register pairs that are shadow registers to each other with different only in MSB | Jun 22, 1993 | Issued |
Array
(
[id] => 3023859
[patent_doc_number] => 05276824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe'
[patent_app_type] => 1
[patent_app_number] => 8/079429
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 079429
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/079429 | Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe | Jun 20, 1993 | Issued |
Array
(
[id] => 3626899
[patent_doc_number] => 05511210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Vector processing device using address data and mask information to generate signal that indicates which addresses are to be accessed from the main memory'
[patent_app_type] => 1
[patent_app_number] => 8/077739
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 077739
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077739 | Vector processing device using address data and mask information to generate signal that indicates which addresses are to be accessed from the main memory | Jun 17, 1993 | Issued |
| 08/079097 | INTEGRATED DATA PROCESSING SYSTEM INCLUDING CPU CORE AND PARALLEL, INDEPENDENTLY OPERATING DSP MODULE | Jun 16, 1993 | Pending |
| 08/075175 | INTEGRATED DATA PROCESSING SYSTEM INCLUDING CPU CORE AND PARALLEL, INDEPENDENTLY OPERATING DSP MODULE UTILIZING PWM FOR PARALLEL DISCONNECT | Jun 9, 1993 | Pending |
Array
(
[id] => 3107165
[patent_doc_number] => 05369777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Integrated digital processing apparatus having a single biodirectional data bus for accommodating a plurality of peripheral devices connected to a plurality of external buses'
[patent_app_type] => 1
[patent_app_number] => 8/071940
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 071940
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/071940 | Integrated digital processing apparatus having a single biodirectional data bus for accommodating a plurality of peripheral devices connected to a plurality of external buses | Jun 2, 1993 | Issued |
| 08/071390 | COMPUTER-IMPLEMENTED PROCESS OF EXTRACTING AND PROCESSING INFORMATION IN A VERTICAL INTERVAL OF A VIDEO SIGNAL | May 31, 1993 | Pending |
| 08/068119 | INTEGRATED DATA PROCESSING SYSTEM INCLUDING CPU CORE AND PARALLEL, INDEPENDENTLY OPERATING DSP MODULE AND HAVING MULTIPLE OPERATING MODES | May 26, 1993 | Pending |
| 08/067545 | MECHANISM FOR HANDLING NON-MASKABLE INTERRUPT REQUESTS RECEIVED FROM DIFFERENT SOURCES | May 25, 1993 | Pending |
Array
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[id] => 3129859
[patent_doc_number] => 05410723
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell'
[patent_app_type] => 1
[patent_app_number] => 8/064781
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[patent_app_date] => 1993-05-21
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[pdf_file] => patents/05/410/05410723.pdf
[firstpage_image] =>[orig_patent_app_number] => 064781
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/064781 | Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell | May 20, 1993 | Issued |
| 08/063412 | PARALLEL INTEGRATED DSP MODULE AND CPU CORE OPERABLE IN DIFFERENT ASYNCHRONOUS FRQUENCIES | May 17, 1993 | Pending |
| 08/060611 | INTEGRATED CPU CORE AND PARALLEL, INDEPENDENTLY OPERATING DSP MODULE WITH QAM/TCM MODEM ALGORITHM | May 11, 1993 | Pending |
| 08/063859 | LATTICE FILTER AND INVERSE LATTICE FILTER USING DSP INSTRUCTION PAIR | May 11, 1993 | Pending |
Array
(
[id] => 3530035
[patent_doc_number] => 05506994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Multiprocessor-type one-chip microcomputer with dual-mode functional terminals'
[patent_app_type] => 1
[patent_app_number] => 8/049720
[patent_app_country] => US
[patent_app_date] => 1993-04-20
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[firstpage_image] =>[orig_patent_app_number] => 049720
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/049720 | Multiprocessor-type one-chip microcomputer with dual-mode functional terminals | Apr 19, 1993 | Issued |
| 08/047800 | PROGRAMMABLE LOGIC HAVING SELECTABLE OUTPUT STATES FOR INITIALIZATION AND RESETS | Apr 14, 1993 | Pending |
Array
(
[id] => 3682143
[patent_doc_number] => 05600844
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Single chip integrated circuit system architecture for document installation set computing'
[patent_app_type] => 1
[patent_app_number] => 8/043625
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[patent_app_date] => 1993-04-05
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[firstpage_image] =>[orig_patent_app_number] => 043625
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/043625 | Single chip integrated circuit system architecture for document installation set computing | Apr 4, 1993 | Issued |
Array
(
[id] => 3507475
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode'
[patent_app_type] => 1
[patent_app_number] => 8/034300
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[firstpage_image] =>[orig_patent_app_number] => 034300
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/034300 | Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode | Mar 21, 1993 | Issued |
Array
(
[id] => 3564611
[patent_doc_number] => 05493669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/025453 | Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits | Mar 2, 1993 | Issued |
