Search

Alecia Diane English

Examiner (ID: 3829, Phone: (571)270-1595 , Office: P/2625 )

Most Active Art Unit
2625
Art Unit(s)
2629, 2775, 2699, 2675, 2625
Total Applications
715
Issued Applications
341
Pending Applications
80
Abandoned Applications
303

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3051009 [patent_doc_number] => 05301350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Real time storage/retrieval subsystem for document processing in banking operations' [patent_app_type] => 1 [patent_app_number] => 8/000909 [patent_app_country] => US [patent_app_date] => 1993-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 28475 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301350.pdf [firstpage_image] =>[orig_patent_app_number] => 000909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000909
Real time storage/retrieval subsystem for document processing in banking operations Jan 5, 1993 Issued
Array ( [id] => 3123213 [patent_doc_number] => 05408676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Parallel data processing system with plural-system bus configuration capable of fast data communication between processors by using common buses' [patent_app_type] => 1 [patent_app_number] => 7/998532 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408676.pdf [firstpage_image] =>[orig_patent_app_number] => 998532 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998532
Parallel data processing system with plural-system bus configuration capable of fast data communication between processors by using common buses Dec 29, 1992 Issued
Array ( [id] => 3123176 [patent_doc_number] => 05408674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size' [patent_app_type] => 1 [patent_app_number] => 7/995772 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4923 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408674.pdf [firstpage_image] =>[orig_patent_app_number] => 995772 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995772
System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size Dec 22, 1992 Issued
Array ( [id] => 3427427 [patent_doc_number] => 05454115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Data driven type processor having data flow program divided into plurality of simultaneously executable program groups for an N:1 read-out to memory-access ratio' [patent_app_type] => 1 [patent_app_number] => 7/995699 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 6687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454115.pdf [firstpage_image] =>[orig_patent_app_number] => 995699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995699
Data driven type processor having data flow program divided into plurality of simultaneously executable program groups for an N:1 read-out to memory-access ratio Dec 22, 1992 Issued
Array ( [id] => 3428384 [patent_doc_number] => 05394556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Method and apparatus for unique address assignment, node self-identification and topology mapping for a directed acyclic graph' [patent_app_type] => 1 [patent_app_number] => 7/994402 [patent_app_country] => US [patent_app_date] => 1992-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7164 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394556.pdf [firstpage_image] =>[orig_patent_app_number] => 994402 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994402
Method and apparatus for unique address assignment, node self-identification and topology mapping for a directed acyclic graph Dec 20, 1992 Issued
Array ( [id] => 3133756 [patent_doc_number] => 05450604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Data rotation using parallel to serial units that receive data from memory units and rotation buffer that provides rotated data to memory units' [patent_app_type] => 1 [patent_app_number] => 7/994490 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 15572 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450604.pdf [firstpage_image] =>[orig_patent_app_number] => 994490 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994490
Data rotation using parallel to serial units that receive data from memory units and rotation buffer that provides rotated data to memory units Dec 17, 1992 Issued
Array ( [id] => 3495838 [patent_doc_number] => 05446909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand' [patent_app_type] => 1 [patent_app_number] => 7/989219 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3806 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446909.pdf [firstpage_image] =>[orig_patent_app_number] => 989219 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989219
Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand Dec 10, 1992 Issued
Array ( [id] => 3465333 [patent_doc_number] => 05379403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Method and interface adapter for interfacing an ISA board to an MCA system by the issuance of an ILLINI-CDCHRDY signal from the interface adapter' [patent_app_type] => 1 [patent_app_number] => 7/983500 [patent_app_country] => US [patent_app_date] => 1992-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2825 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379403.pdf [firstpage_image] =>[orig_patent_app_number] => 983500 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/983500
Method and interface adapter for interfacing an ISA board to an MCA system by the issuance of an ILLINI-CDCHRDY signal from the interface adapter Nov 26, 1992 Issued
07/980392 BLOCK TRANSFER CONTROLLER FETCH Nov 22, 1992 Abandoned
07/966011 PROGRAMMABLE CONTROLLER FOR HIGH-SPEED ARITHMETIC OPERATIONS Oct 22, 1992 Abandoned
Array ( [id] => 3529822 [patent_doc_number] => 05506980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory' [patent_app_type] => 1 [patent_app_number] => 7/964845 [patent_app_country] => US [patent_app_date] => 1992-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11938 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506980.pdf [firstpage_image] =>[orig_patent_app_number] => 964845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964845
Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory Oct 21, 1992 Issued
Array ( [id] => 3436961 [patent_doc_number] => 05404424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Normalized proportional synchronous bandwidth allocation in a token ring network by setting a maximum message transmission time' [patent_app_type] => 1 [patent_app_number] => 7/949043 [patent_app_country] => US [patent_app_date] => 1992-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4113 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404424.pdf [firstpage_image] =>[orig_patent_app_number] => 949043 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/949043
Normalized proportional synchronous bandwidth allocation in a token ring network by setting a maximum message transmission time Sep 21, 1992 Issued
Array ( [id] => 3053139 [patent_doc_number] => 05377333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers' [patent_app_type] => 1 [patent_app_number] => 7/945483 [patent_app_country] => US [patent_app_date] => 1992-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 11554 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377333.pdf [firstpage_image] =>[orig_patent_app_number] => 945483 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/945483
Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers Sep 14, 1992 Issued
07/943542 CENTRALIZED RESOUCE SUPERVISING SYSTEM FOR A DISTRIBUTED DATA NETWORK Sep 10, 1992 Abandoned
Array ( [id] => 3111718 [patent_doc_number] => 05319791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'System for predicting memory fault in vector processor by sensing indication signal to scalar processor to continue a next vector instruction issuance' [patent_app_type] => 1 [patent_app_number] => 7/943165 [patent_app_country] => US [patent_app_date] => 1992-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8003 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319791.pdf [firstpage_image] =>[orig_patent_app_number] => 943165 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/943165
System for predicting memory fault in vector processor by sensing indication signal to scalar processor to continue a next vector instruction issuance Sep 9, 1992 Issued
07/928360 COOPERATIVE OPERATION USING WORKSTATIONS HAVING OPERATIVE RIGHTS ASSIGNED Aug 11, 1992 Abandoned
07/926265 PARALLEL COMPUTER WITH TIME SHARING CAPABILITY Aug 4, 1992 Abandoned
Array ( [id] => 3122903 [patent_doc_number] => 05408664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'System and Method for booting computer for operation in either of two byte-order modes' [patent_app_type] => 1 [patent_app_number] => 7/901910 [patent_app_country] => US [patent_app_date] => 1992-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2978 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408664.pdf [firstpage_image] =>[orig_patent_app_number] => 901910 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/901910
System and Method for booting computer for operation in either of two byte-order modes Jun 18, 1992 Issued
Array ( [id] => 3494807 [patent_doc_number] => 05446841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Multi-processor system having shared memory for storing the communication information used in communicating between processors' [patent_app_type] => 1 [patent_app_number] => 7/898688 [patent_app_country] => US [patent_app_date] => 1992-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6287 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446841.pdf [firstpage_image] =>[orig_patent_app_number] => 898688 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/898688
Multi-processor system having shared memory for storing the communication information used in communicating between processors Jun 14, 1992 Issued
Array ( [id] => 3592305 [patent_doc_number] => 05499342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'System for dynamically switching logical sessions between terminal device and a processor which stops its operation to another working processor under control of communication control processor' [patent_app_type] => 1 [patent_app_number] => 7/867988 [patent_app_country] => US [patent_app_date] => 1992-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9001 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499342.pdf [firstpage_image] =>[orig_patent_app_number] => 867988 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/867988
System for dynamically switching logical sessions between terminal device and a processor which stops its operation to another working processor under control of communication control processor Apr 30, 1992 Issued
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