Search

Alecia Diane English

Examiner (ID: 3829, Phone: (571)270-1595 , Office: P/2625 )

Most Active Art Unit
2625
Art Unit(s)
2629, 2775, 2699, 2675, 2625
Total Applications
715
Issued Applications
341
Pending Applications
80
Abandoned Applications
303

Applications

Application numberTitle of the applicationFiling DateStatus
07/687714 MICROPROCESSOR FOR INSERTING A BUS CYCLE IN AN INSTRUCTION SET TO OUTPUT AN INTERNAL INFORMATION FOR AN EMULATION Apr 17, 1991 Abandoned
Array ( [id] => 3050080 [patent_doc_number] => 05301303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Communication system concentrator configurable to different access methods' [patent_app_type] => 1 [patent_app_number] => 7/687590 [patent_app_country] => US [patent_app_date] => 1991-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 42 [patent_no_of_words] => 16052 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301303.pdf [firstpage_image] =>[orig_patent_app_number] => 687590 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/687590
Communication system concentrator configurable to different access methods Apr 15, 1991 Issued
Array ( [id] => 3042580 [patent_doc_number] => 05317755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection' [patent_app_type] => 1 [patent_app_number] => 7/683002 [patent_app_country] => US [patent_app_date] => 1991-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 53 [patent_no_of_words] => 15025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317755.pdf [firstpage_image] =>[orig_patent_app_number] => 683002 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/683002
Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection Apr 9, 1991 Issued
07/676110 PROGRAMMABLE MICROPROCESSOR HAVING SECURITY FUNCTION Mar 26, 1991 Abandoned
Array ( [id] => 3024145 [patent_doc_number] => 05276839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'System for programming EEPROM with data loaded in ROM by sending switch signal to isolate EEPROM from host system' [patent_app_type] => 1 [patent_app_number] => 7/667619 [patent_app_country] => US [patent_app_date] => 1991-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4199 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276839.pdf [firstpage_image] =>[orig_patent_app_number] => 667619 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/667619
System for programming EEPROM with data loaded in ROM by sending switch signal to isolate EEPROM from host system Mar 6, 1991 Issued
07/666039 SYSTEM AND METHOD FOR EXECUTING AND DEBUGGING MULTIPLE CODES IN A MULTI-ARCHITECTURE A ENVIRONMENT Mar 6, 1991 Abandoned
Array ( [id] => 3090363 [patent_doc_number] => 05297291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'System for linking program units by binding symbol vector index in the symbol table into calling image to obtain current value of the target image' [patent_app_type] => 1 [patent_app_number] => 7/666023 [patent_app_country] => US [patent_app_date] => 1991-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4257 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297291.pdf [firstpage_image] =>[orig_patent_app_number] => 666023 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/666023
System for linking program units by binding symbol vector index in the symbol table into calling image to obtain current value of the target image Mar 6, 1991 Issued
Array ( [id] => 3077964 [patent_doc_number] => 05295250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input' [patent_app_type] => 1 [patent_app_number] => 7/659606 [patent_app_country] => US [patent_app_date] => 1991-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 2221 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295250.pdf [firstpage_image] =>[orig_patent_app_number] => 659606 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/659606
Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input Feb 20, 1991 Issued
Array ( [id] => 2963521 [patent_doc_number] => 05263149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles' [patent_app_type] => 1 [patent_app_number] => 7/657705 [patent_app_country] => US [patent_app_date] => 1991-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3554 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263149.pdf [firstpage_image] =>[orig_patent_app_number] => 657705 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/657705
Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles Feb 18, 1991 Issued
Array ( [id] => 2977763 [patent_doc_number] => 05274833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Data-flow processor having timer control mechanism for effecting time control processing by creating or introducing timer packet into data path' [patent_app_type] => 1 [patent_app_number] => 7/647710 [patent_app_country] => US [patent_app_date] => 1991-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 4355 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274833.pdf [firstpage_image] =>[orig_patent_app_number] => 647710 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/647710
Data-flow processor having timer control mechanism for effecting time control processing by creating or introducing timer packet into data path Jan 27, 1991 Issued
Array ( [id] => 3032491 [patent_doc_number] => 05303350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Circuit for initializing registers using two input signals for writing default value into D-latch after a reset operation' [patent_app_type] => 1 [patent_app_number] => 7/632172 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303350.pdf [firstpage_image] =>[orig_patent_app_number] => 632172 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/632172
Circuit for initializing registers using two input signals for writing default value into D-latch after a reset operation Dec 19, 1990 Issued
07/628761 COMMUNICATION APPARATUS OPERATIVE TO SWITCH DYNAMICALLY BETWEEN DIFFERENT COMMUNICATION MATING UNIT CONFIGURATIONS Dec 16, 1990 Abandoned
Array ( [id] => 3106929 [patent_doc_number] => 05313598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Method for changing non-leaf entry in tree structure of OSI directory information by sequentially issuing OSI directory commands for the non-leaf entry and lower entries associated therewith in response to decoded change command' [patent_app_type] => 1 [patent_app_number] => 7/627866 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3512 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313598.pdf [firstpage_image] =>[orig_patent_app_number] => 627866 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/627866
Method for changing non-leaf entry in tree structure of OSI directory information by sequentially issuing OSI directory commands for the non-leaf entry and lower entries associated therewith in response to decoded change command Dec 16, 1990 Issued
Array ( [id] => 3007894 [patent_doc_number] => 05367678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically' [patent_app_type] => 1 [patent_app_number] => 7/624376 [patent_app_country] => US [patent_app_date] => 1990-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4770 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367678.pdf [firstpage_image] =>[orig_patent_app_number] => 624376 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624376
Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically Dec 5, 1990 Issued
Array ( [id] => 2904684 [patent_doc_number] => 05210827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Nest level judging device for judging the starting and the end addresses' [patent_app_type] => 1 [patent_app_number] => 7/621715 [patent_app_country] => US [patent_app_date] => 1990-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6424 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210827.pdf [firstpage_image] =>[orig_patent_app_number] => 621715 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/621715
Nest level judging device for judging the starting and the end addresses Dec 4, 1990 Issued
Array ( [id] => 2977153 [patent_doc_number] => 05274798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Electronic apparatus with communication function having power source system with two voltage output levels' [patent_app_type] => 1 [patent_app_number] => 7/618106 [patent_app_country] => US [patent_app_date] => 1990-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 16383 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274798.pdf [firstpage_image] =>[orig_patent_app_number] => 618106 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/618106
Electronic apparatus with communication function having power source system with two voltage output levels Nov 25, 1990 Issued
Array ( [id] => 3102912 [patent_doc_number] => 05278972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Communication system for converting ISDN signaling protocol between local and public network having first group of mandatory elements and second group of non-mandatory elements' [patent_app_type] => 1 [patent_app_number] => 7/616961 [patent_app_country] => US [patent_app_date] => 1990-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6110 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278972.pdf [firstpage_image] =>[orig_patent_app_number] => 616961 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/616961
Communication system for converting ISDN signaling protocol between local and public network having first group of mandatory elements and second group of non-mandatory elements Nov 20, 1990 Issued
Array ( [id] => 2998838 [patent_doc_number] => 05251313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'Method of bit rate adaption using the ECMA 102 protocol' [patent_app_type] => 1 [patent_app_number] => 7/615661 [patent_app_country] => US [patent_app_date] => 1990-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 10456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/251/05251313.pdf [firstpage_image] =>[orig_patent_app_number] => 615661 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/615661
Method of bit rate adaption using the ECMA 102 protocol Nov 18, 1990 Issued
Array ( [id] => 3023824 [patent_doc_number] => 05276822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'System with enhanced execution of address-conflicting instructions using immediate data latch for holding immediate data of a preceding instruction' [patent_app_type] => 1 [patent_app_number] => 7/612731 [patent_app_country] => US [patent_app_date] => 1990-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10827 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276822.pdf [firstpage_image] =>[orig_patent_app_number] => 612731 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/612731
System with enhanced execution of address-conflicting instructions using immediate data latch for holding immediate data of a preceding instruction Nov 13, 1990 Issued
Array ( [id] => 3059717 [patent_doc_number] => 05287532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte' [patent_app_type] => 1 [patent_app_number] => 7/613217 [patent_app_country] => US [patent_app_date] => 1990-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2634 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287532.pdf [firstpage_image] =>[orig_patent_app_number] => 613217 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/613217
Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte Nov 13, 1990 Issued
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