Search

Alecia Diane English

Examiner (ID: 3829, Phone: (571)270-1595 , Office: P/2625 )

Most Active Art Unit
2625
Art Unit(s)
2629, 2775, 2699, 2675, 2625
Total Applications
715
Issued Applications
341
Pending Applications
80
Abandoned Applications
303

Applications

Application numberTitle of the applicationFiling DateStatus
07/610573 AN ELECTRONIC FILING SYSTEM USING A MARK ON EACH PAGE OF THE DOCUMENT FOR BUILDING A DATABASE WITH RESPECT TO PLURALITY OF MULTI-PAGE DOCUMENTS Nov 7, 1990 Abandoned
Array ( [id] => 3761126 [patent_doc_number] => 05717928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description' [patent_app_type] => 1 [patent_app_number] => 7/610479 [patent_app_country] => US [patent_app_date] => 1990-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717928.pdf [firstpage_image] =>[orig_patent_app_number] => 610479 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/610479
System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description Nov 6, 1990 Issued
07/609814 PROCESSOR WITH IN-SYSTEM EMULATION CIRCUITRY AND METHOD Nov 5, 1990 Abandoned
07/608914 DATA-DRIVEN ARRAY PROCESSOR WITH HANDSHAKING PROTOCOL Nov 4, 1990 Abandoned
Array ( [id] => 3028735 [patent_doc_number] => 05341505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'System and method for accessing remotely located ZIP+4 zipcode database' [patent_app_type] => 1 [patent_app_number] => 7/605649 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341505.pdf [firstpage_image] =>[orig_patent_app_number] => 605649 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605649
System and method for accessing remotely located ZIP+4 zipcode database Oct 29, 1990 Issued
Array ( [id] => 2889055 [patent_doc_number] => 05185883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'System for locating failure signals by comparing input data with stored threshold value and storing failure addresses in alternating buffers' [patent_app_type] => 1 [patent_app_number] => 7/603791 [patent_app_country] => US [patent_app_date] => 1990-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3737 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185883.pdf [firstpage_image] =>[orig_patent_app_number] => 603791 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/603791
System for locating failure signals by comparing input data with stored threshold value and storing failure addresses in alternating buffers Oct 25, 1990 Issued
Array ( [id] => 3094918 [patent_doc_number] => 05280595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections' [patent_app_type] => 1 [patent_app_number] => 7/593923 [patent_app_country] => US [patent_app_date] => 1990-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9240 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280595.pdf [firstpage_image] =>[orig_patent_app_number] => 593923 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/593923
State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections Oct 4, 1990 Issued
Array ( [id] => 2902171 [patent_doc_number] => 05239658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Switchable parallel bus terminator having stable terminator voltage with respect to ambient temperature change' [patent_app_type] => 1 [patent_app_number] => 7/588103 [patent_app_country] => US [patent_app_date] => 1990-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1311 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239658.pdf [firstpage_image] =>[orig_patent_app_number] => 588103 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588103
Switchable parallel bus terminator having stable terminator voltage with respect to ambient temperature change Sep 24, 1990 Issued
Array ( [id] => 3088762 [patent_doc_number] => 05323488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Memory access method and circuit in which access timing to a memory is divided into N periods to be accessed from N access request sources' [patent_app_type] => 1 [patent_app_number] => 7/582009 [patent_app_country] => US [patent_app_date] => 1990-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5454 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323488.pdf [firstpage_image] =>[orig_patent_app_number] => 582009 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/582009
Memory access method and circuit in which access timing to a memory is divided into N periods to be accessed from N access request sources Sep 13, 1990 Issued
Array ( [id] => 2947832 [patent_doc_number] => 05247625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'System for checking undefined addressing prescribed for each instruction of variable length using tag information to determine addressing field decoded in present or preceding cycle' [patent_app_type] => 1 [patent_app_number] => 7/580791 [patent_app_country] => US [patent_app_date] => 1990-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3821 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247625.pdf [firstpage_image] =>[orig_patent_app_number] => 580791 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/580791
System for checking undefined addressing prescribed for each instruction of variable length using tag information to determine addressing field decoded in present or preceding cycle Sep 10, 1990 Issued
07/578976 EFFICIENT EXECUTION OF PROGRAMS WITH CONDITIONAL BRANCHES ON VERY LONG INSTRUCTION WORD MACHINES Sep 4, 1990 Abandoned
07/576012 INTEGRATED DIGITAL PROCESSING APPARATUS HAVING A SINGLE INTERNAL BIDIRECTIONAL DATA BUS Aug 30, 1990 Abandoned
Array ( [id] => 3090044 [patent_doc_number] => 05297273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two' [patent_app_type] => 1 [patent_app_number] => 7/574976 [patent_app_country] => US [patent_app_date] => 1990-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2727 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297273.pdf [firstpage_image] =>[orig_patent_app_number] => 574976 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574976
System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two Aug 29, 1990 Issued
Array ( [id] => 2998590 [patent_doc_number] => 05212779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'System for guarantee reexecution after interruption by conditionally used store buffer if microinstruction being executed is a memory write and last microinstruction' [patent_app_type] => 1 [patent_app_number] => 7/574845 [patent_app_country] => US [patent_app_date] => 1990-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 14154 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212779.pdf [firstpage_image] =>[orig_patent_app_number] => 574845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574845
System for guarantee reexecution after interruption by conditionally used store buffer if microinstruction being executed is a memory write and last microinstruction Aug 28, 1990 Issued
Array ( [id] => 2961506 [patent_doc_number] => 05222219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Pipeline computer system having write order preservation' [patent_app_type] => 1 [patent_app_number] => 7/574389 [patent_app_country] => US [patent_app_date] => 1990-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1234 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222219.pdf [firstpage_image] =>[orig_patent_app_number] => 574389 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574389
Pipeline computer system having write order preservation Aug 26, 1990 Issued
Array ( [id] => 2951596 [patent_doc_number] => 05261081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Sequence control apparatus for producing output signals in synchronous with a consistent delay from rising or falling edge of clock input signal' [patent_app_type] => 1 [patent_app_number] => 7/557811 [patent_app_country] => US [patent_app_date] => 1990-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4756 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261081.pdf [firstpage_image] =>[orig_patent_app_number] => 557811 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557811
Sequence control apparatus for producing output signals in synchronous with a consistent delay from rising or falling edge of clock input signal Jul 25, 1990 Issued
Array ( [id] => 2930141 [patent_doc_number] => 05193174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'System for automatically redirecting information to alternate system console in response to the comparison of present and default system configuration in personal computer system' [patent_app_type] => 1 [patent_app_number] => 7/557035 [patent_app_country] => US [patent_app_date] => 1990-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6389 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193174.pdf [firstpage_image] =>[orig_patent_app_number] => 557035 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557035
System for automatically redirecting information to alternate system console in response to the comparison of present and default system configuration in personal computer system Jul 22, 1990 Issued
Array ( [id] => 2924892 [patent_doc_number] => 05228137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method for controlling execution of host computer application programs through a second computer by establishing relevant parameters having variable time of occurrence and context' [patent_app_type] => 1 [patent_app_number] => 7/549889 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14739 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228137.pdf [firstpage_image] =>[orig_patent_app_number] => 549889 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549889
Method for controlling execution of host computer application programs through a second computer by establishing relevant parameters having variable time of occurrence and context Jul 8, 1990 Issued
07/547127 DATA COMMUNICATION APPARATUS FOR DESIGNATING A COMMUNICATION CONDITION AND A DESIGNATION STATION TO WHICH DATA IS TRANSMITTED Jul 2, 1990 Abandoned
Array ( [id] => 2946620 [patent_doc_number] => 05197132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery' [patent_app_type] => 1 [patent_app_number] => 7/546411 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9930 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197132.pdf [firstpage_image] =>[orig_patent_app_number] => 546411 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546411
Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery Jun 28, 1990 Issued
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