Search

Alecia Diane English

Examiner (ID: 3829, Phone: (571)270-1595 , Office: P/2625 )

Most Active Art Unit
2625
Art Unit(s)
2629, 2775, 2699, 2675, 2625
Total Applications
715
Issued Applications
341
Pending Applications
80
Abandoned Applications
303

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3059606 [patent_doc_number] => 05287526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'System for selectively modifying codes generated by a touch type keyboard upon detecting predetermined sequence of make/break codes and expiration of predefined time interval' [patent_app_type] => 1 [patent_app_number] => 7/542482 [patent_app_country] => US [patent_app_date] => 1990-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8079 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287526.pdf [firstpage_image] =>[orig_patent_app_number] => 542482 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542482
System for selectively modifying codes generated by a touch type keyboard upon detecting predetermined sequence of make/break codes and expiration of predefined time interval Jun 21, 1990 Issued
Array ( [id] => 3025311 [patent_doc_number] => 05276897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'System for determining propositional logic theorems by applying values and rules to triplets that are generated from boolean formula' [patent_app_type] => 1 [patent_app_number] => 7/537937 [patent_app_country] => US [patent_app_date] => 1990-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8869 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276897.pdf [firstpage_image] =>[orig_patent_app_number] => 537937 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/537937
System for determining propositional logic theorems by applying values and rules to triplets that are generated from boolean formula Jun 13, 1990 Issued
Array ( [id] => 2946654 [patent_doc_number] => 05197134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Pipeline processor for performing write instruction by referring to cache memory search result obtained during idling state of operand reading cycle' [patent_app_type] => 1 [patent_app_number] => 7/525774 [patent_app_country] => US [patent_app_date] => 1990-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1437 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197134.pdf [firstpage_image] =>[orig_patent_app_number] => 525774 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/525774
Pipeline processor for performing write instruction by referring to cache memory search result obtained during idling state of operand reading cycle May 20, 1990 Issued
Array ( [id] => 2952056 [patent_doc_number] => 05261105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'System for transferring blocks of data among diverse units having cycle identifier signals to identify different phase of data transfer operations' [patent_app_type] => 1 [patent_app_number] => 7/518894 [patent_app_country] => US [patent_app_date] => 1990-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6749 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261105.pdf [firstpage_image] =>[orig_patent_app_number] => 518894 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/518894
System for transferring blocks of data among diverse units having cycle identifier signals to identify different phase of data transfer operations May 3, 1990 Issued
Array ( [id] => 2988292 [patent_doc_number] => 05226123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'System for addressing multiple addressable units by inactivating previous units and automatically change the impedance of the connecting cable' [patent_app_type] => 1 [patent_app_number] => 7/499368 [patent_app_country] => US [patent_app_date] => 1990-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226123.pdf [firstpage_image] =>[orig_patent_app_number] => 499368 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/499368
System for addressing multiple addressable units by inactivating previous units and automatically change the impedance of the connecting cable Mar 25, 1990 Issued
Array ( [id] => 3495195 [patent_doc_number] => 05446865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Processor adapted for sharing memory with more than one type of processor' [patent_app_type] => 1 [patent_app_number] => 7/493018 [patent_app_country] => US [patent_app_date] => 1990-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 21229 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446865.pdf [firstpage_image] =>[orig_patent_app_number] => 493018 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/493018
Processor adapted for sharing memory with more than one type of processor Mar 12, 1990 Issued
Array ( [id] => 2928008 [patent_doc_number] => 05179697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'System for deleting prioritized data stored in second memory after all the data has been successfully transferred to first memory' [patent_app_type] => 1 [patent_app_number] => 7/489782 [patent_app_country] => US [patent_app_date] => 1990-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2138 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179697.pdf [firstpage_image] =>[orig_patent_app_number] => 489782 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/489782
System for deleting prioritized data stored in second memory after all the data has been successfully transferred to first memory Mar 4, 1990 Issued
Array ( [id] => 2888812 [patent_doc_number] => 05185872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy' [patent_app_type] => 1 [patent_app_number] => 7/486407 [patent_app_country] => US [patent_app_date] => 1990-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8472 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185872.pdf [firstpage_image] =>[orig_patent_app_number] => 486407 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/486407
System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy Feb 27, 1990 Issued
Array ( [id] => 3487372 [patent_doc_number] => 05428801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Data array conversion control system for controlling conversion of data arrays being transferred between two processing systems' [patent_app_type] => 1 [patent_app_number] => 7/485654 [patent_app_country] => US [patent_app_date] => 1990-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2203 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428801.pdf [firstpage_image] =>[orig_patent_app_number] => 485654 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/485654
Data array conversion control system for controlling conversion of data arrays being transferred between two processing systems Feb 26, 1990 Issued
Array ( [id] => 2888744 [patent_doc_number] => 05185869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'System for masking execution ready signal during unsettled period of determining branch condition to prevent reading out of stored instructions' [patent_app_type] => 1 [patent_app_number] => 7/474263 [patent_app_country] => US [patent_app_date] => 1990-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6102 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185869.pdf [firstpage_image] =>[orig_patent_app_number] => 474263 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/474263
System for masking execution ready signal during unsettled period of determining branch condition to prevent reading out of stored instructions Feb 4, 1990 Issued
Array ( [id] => 2961799 [patent_doc_number] => 05222235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Databases system for permitting concurrent indexing and reloading of data by early simulating the reload process to determine final locations of the data' [patent_app_type] => 1 [patent_app_number] => 7/473663 [patent_app_country] => US [patent_app_date] => 1990-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7793 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222235.pdf [firstpage_image] =>[orig_patent_app_number] => 473663 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/473663
Databases system for permitting concurrent indexing and reloading of data by early simulating the reload process to determine final locations of the data Jan 31, 1990 Issued
07/461876 A DATA PROCESSOR HAVING A MULTI- STAGE INSTRUCTION PIPE SELECTING LOGIC RESPONSIVE TO AN INSTRUSTION DECODER FOR SELECTING ONE STAGE OF THE INSTRUCTION PIPE Jan 7, 1990 Abandoned
07/457561 CONTROL SYSTEM FOR FETCHING AN INSTRUCTION Dec 26, 1989 Abandoned
Array ( [id] => 2888780 [patent_doc_number] => 05185871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions' [patent_app_type] => 1 [patent_app_number] => 7/457222 [patent_app_country] => US [patent_app_date] => 1989-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 21446 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185871.pdf [firstpage_image] =>[orig_patent_app_number] => 457222 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/457222
Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions Dec 25, 1989 Issued
Array ( [id] => 2980312 [patent_doc_number] => 05202983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'File accessing system using code name to access selected conversion table for converting simplified file name into original file name' [patent_app_type] => 1 [patent_app_number] => 7/452396 [patent_app_country] => US [patent_app_date] => 1989-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2080 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202983.pdf [firstpage_image] =>[orig_patent_app_number] => 452396 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/452396
File accessing system using code name to access selected conversion table for converting simplified file name into original file name Dec 18, 1989 Issued
Array ( [id] => 2925210 [patent_doc_number] => 05237666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction' [patent_app_type] => 1 [patent_app_number] => 7/451252 [patent_app_country] => US [patent_app_date] => 1989-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 13030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237666.pdf [firstpage_image] =>[orig_patent_app_number] => 451252 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/451252
Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction Dec 14, 1989 Issued
Array ( [id] => 2998763 [patent_doc_number] => 05251309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'System for measuring the efficiency of accessing vector elements using interelement distance of vector data or bank conflicts' [patent_app_type] => 1 [patent_app_number] => 7/431188 [patent_app_country] => US [patent_app_date] => 1989-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4562 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/251/05251309.pdf [firstpage_image] =>[orig_patent_app_number] => 431188 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/431188
System for measuring the efficiency of accessing vector elements using interelement distance of vector data or bank conflicts Nov 2, 1989 Issued
07/421494 DISTRIBUTION OF UNIQUE CONSTANTS IN SYNCHRONOUS VECTOR PROCESSOR Oct 12, 1989 Abandoned
07/419566 STORAGE/RETRIEVAL MODULE FOR DOCUMENT PROCESSING SYSTEM Oct 9, 1989 Abandoned
Array ( [id] => 3059507 [patent_doc_number] => 05287520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Monitor system having list of items with fixed time slices for transmitting timing signals at the end of a communication between master processor and slave processors' [patent_app_type] => 1 [patent_app_number] => 7/389000 [patent_app_country] => US [patent_app_date] => 1989-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6623 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287520.pdf [firstpage_image] =>[orig_patent_app_number] => 389000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/389000
Monitor system having list of items with fixed time slices for transmitting timing signals at the end of a communication between master processor and slave processors Aug 2, 1989 Issued
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