| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'System for selectively modifying codes generated by a touch type keyboard upon detecting predetermined sequence of make/break codes and expiration of predefined time interval'
[patent_app_type] => 1
[patent_app_number] => 7/542482
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/542482 | System for selectively modifying codes generated by a touch type keyboard upon detecting predetermined sequence of make/break codes and expiration of predefined time interval | Jun 21, 1990 | Issued |
Array
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[patent_doc_number] => 05276897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'System for determining propositional logic theorems by applying values and rules to triplets that are generated from boolean formula'
[patent_app_type] => 1
[patent_app_number] => 7/537937
[patent_app_country] => US
[patent_app_date] => 1990-06-14
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[firstpage_image] =>[orig_patent_app_number] => 537937
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/537937 | System for determining propositional logic theorems by applying values and rules to triplets that are generated from boolean formula | Jun 13, 1990 | Issued |
Array
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[id] => 2946654
[patent_doc_number] => 05197134
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Pipeline processor for performing write instruction by referring to cache memory search result obtained during idling state of operand reading cycle'
[patent_app_type] => 1
[patent_app_number] => 7/525774
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 525774
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/525774 | Pipeline processor for performing write instruction by referring to cache memory search result obtained during idling state of operand reading cycle | May 20, 1990 | Issued |
Array
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[id] => 2952056
[patent_doc_number] => 05261105
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'System for transferring blocks of data among diverse units having cycle identifier signals to identify different phase of data transfer operations'
[patent_app_type] => 1
[patent_app_number] => 7/518894
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[patent_app_date] => 1990-05-04
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[firstpage_image] =>[orig_patent_app_number] => 518894
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/518894 | System for transferring blocks of data among diverse units having cycle identifier signals to identify different phase of data transfer operations | May 3, 1990 | Issued |
Array
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[id] => 2988292
[patent_doc_number] => 05226123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-06
[patent_title] => 'System for addressing multiple addressable units by inactivating previous units and automatically change the impedance of the connecting cable'
[patent_app_type] => 1
[patent_app_number] => 7/499368
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[patent_app_date] => 1990-03-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/499368 | System for addressing multiple addressable units by inactivating previous units and automatically change the impedance of the connecting cable | Mar 25, 1990 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Processor adapted for sharing memory with more than one type of processor'
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[patent_app_number] => 7/493018
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/493018 | Processor adapted for sharing memory with more than one type of processor | Mar 12, 1990 | Issued |
Array
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[id] => 2928008
[patent_doc_number] => 05179697
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[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'System for deleting prioritized data stored in second memory after all the data has been successfully transferred to first memory'
[patent_app_type] => 1
[patent_app_number] => 7/489782
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[firstpage_image] =>[orig_patent_app_number] => 489782
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/489782 | System for deleting prioritized data stored in second memory after all the data has been successfully transferred to first memory | Mar 4, 1990 | Issued |
Array
(
[id] => 2888812
[patent_doc_number] => 05185872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-09
[patent_title] => 'System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy'
[patent_app_type] => 1
[patent_app_number] => 7/486407
[patent_app_country] => US
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[pdf_file] => patents/05/185/05185872.pdf
[firstpage_image] =>[orig_patent_app_number] => 486407
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/486407 | System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy | Feb 27, 1990 | Issued |
Array
(
[id] => 3487372
[patent_doc_number] => 05428801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'Data array conversion control system for controlling conversion of data arrays being transferred between two processing systems'
[patent_app_type] => 1
[patent_app_number] => 7/485654
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/485654 | Data array conversion control system for controlling conversion of data arrays being transferred between two processing systems | Feb 26, 1990 | Issued |
Array
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[id] => 2888744
[patent_doc_number] => 05185869
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-09
[patent_title] => 'System for masking execution ready signal during unsettled period of determining branch condition to prevent reading out of stored instructions'
[patent_app_type] => 1
[patent_app_number] => 7/474263
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Array
(
[id] => 2961799
[patent_doc_number] => 05222235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-22
[patent_title] => 'Databases system for permitting concurrent indexing and reloading of data by early simulating the reload process to determine final locations of the data'
[patent_app_type] => 1
[patent_app_number] => 7/473663
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/473663 | Databases system for permitting concurrent indexing and reloading of data by early simulating the reload process to determine final locations of the data | Jan 31, 1990 | Issued |
| 07/461876 | A DATA PROCESSOR HAVING A MULTI- STAGE INSTRUCTION PIPE SELECTING LOGIC RESPONSIVE TO AN INSTRUSTION DECODER FOR SELECTING ONE STAGE OF THE INSTRUCTION PIPE | Jan 7, 1990 | Abandoned |
| 07/457561 | CONTROL SYSTEM FOR FETCHING AN INSTRUCTION | Dec 26, 1989 | Abandoned |
Array
(
[id] => 2888780
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[patent_issue_date] => 1993-02-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/457222 | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions | Dec 25, 1989 | Issued |
Array
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[patent_issue_date] => 1993-04-13
[patent_title] => 'File accessing system using code name to access selected conversion table for converting simplified file name into original file name'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/452396 | File accessing system using code name to access selected conversion table for converting simplified file name into original file name | Dec 18, 1989 | Issued |
Array
(
[id] => 2925210
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[patent_kind] => NA
[patent_issue_date] => 1993-08-17
[patent_title] => 'Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/451252 | Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction | Dec 14, 1989 | Issued |
Array
(
[id] => 2998763
[patent_doc_number] => 05251309
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'System for measuring the efficiency of accessing vector elements using interelement distance of vector data or bank conflicts'
[patent_app_type] => 1
[patent_app_number] => 7/431188
[patent_app_country] => US
[patent_app_date] => 1989-11-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/431188 | System for measuring the efficiency of accessing vector elements using interelement distance of vector data or bank conflicts | Nov 2, 1989 | Issued |
| 07/421494 | DISTRIBUTION OF UNIQUE CONSTANTS IN SYNCHRONOUS VECTOR PROCESSOR | Oct 12, 1989 | Abandoned |
| 07/419566 | STORAGE/RETRIEVAL MODULE FOR DOCUMENT PROCESSING SYSTEM | Oct 9, 1989 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/389000 | Monitor system having list of items with fixed time slices for transmitting timing signals at the end of a communication between master processor and slave processors | Aug 2, 1989 | Issued |