Search

Alecia Diane English

Examiner (ID: 3829, Phone: (571)270-1595 , Office: P/2625 )

Most Active Art Unit
2625
Art Unit(s)
2629, 2775, 2699, 2675, 2625
Total Applications
715
Issued Applications
341
Pending Applications
80
Abandoned Applications
303

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3825847 [patent_doc_number] => 05832216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Network adapter having single ported memory which is accessible by network and peripheral bus on a time division multiplexed (TDM) basis' [patent_app_type] => 1 [patent_app_number] => 8/859519 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1212 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832216.pdf [firstpage_image] =>[orig_patent_app_number] => 859519 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859519
Network adapter having single ported memory which is accessible by network and peripheral bus on a time division multiplexed (TDM) basis May 19, 1997 Issued
Array ( [id] => 3778323 [patent_doc_number] => 05845072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method and apparatus for parallel and pipelining transference of data between integrated circuits using a common macro interface' [patent_app_type] => 1 [patent_app_number] => 8/850284 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845072.pdf [firstpage_image] =>[orig_patent_app_number] => 850284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850284
Method and apparatus for parallel and pipelining transference of data between integrated circuits using a common macro interface May 4, 1997 Issued
Array ( [id] => 3830482 [patent_doc_number] => 05812839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit' [patent_app_type] => 1 [patent_app_number] => 8/851141 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8619 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812839.pdf [firstpage_image] =>[orig_patent_app_number] => 851141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851141
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit May 4, 1997 Issued
Array ( [id] => 3855243 [patent_doc_number] => 05708842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Apparatus for changing coefficients utilized to perform a convolution operation having address generator which uses initial count number and up/down count inputs received from external' [patent_app_type] => 1 [patent_app_number] => 8/822770 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3982 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708842.pdf [firstpage_image] =>[orig_patent_app_number] => 822770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822770
Apparatus for changing coefficients utilized to perform a convolution operation having address generator which uses initial count number and up/down count inputs received from external Mar 20, 1997 Issued
Array ( [id] => 3796519 [patent_doc_number] => 05819054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Storage system realizing scalability and fault tolerance' [patent_app_type] => 1 [patent_app_number] => 8/819625 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 7436 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819054.pdf [firstpage_image] =>[orig_patent_app_number] => 819625 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819625
Storage system realizing scalability and fault tolerance Mar 16, 1997 Issued
Array ( [id] => 3830006 [patent_doc_number] => 05812806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Data driven information processor configuring each data packet with a multi-attribute tag having at least two components' [patent_app_type] => 1 [patent_app_number] => 8/784769 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6610 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812806.pdf [firstpage_image] =>[orig_patent_app_number] => 784769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/784769
Data driven information processor configuring each data packet with a multi-attribute tag having at least two components Jan 15, 1997 Issued
Array ( [id] => 3757710 [patent_doc_number] => 05754762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Secure multiple application IC card using interrupt instruction issued by operating system or application program to control operation flag that determines the operational mode of bi-modal CPU' [patent_app_type] => 1 [patent_app_number] => 8/782063 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754762.pdf [firstpage_image] =>[orig_patent_app_number] => 782063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782063
Secure multiple application IC card using interrupt instruction issued by operating system or application program to control operation flag that determines the operational mode of bi-modal CPU Jan 12, 1997 Issued
Array ( [id] => 3858983 [patent_doc_number] => 05745758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'System for regulating multicomputer data transfer by allocating time slot to designated processing task according to communication bandwidth capabilities and modifying time slots when bandwidth change' [patent_app_type] => 1 [patent_app_number] => 8/781243 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 17192 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745758.pdf [firstpage_image] =>[orig_patent_app_number] => 781243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781243
System for regulating multicomputer data transfer by allocating time slot to designated processing task according to communication bandwidth capabilities and modifying time slots when bandwidth change Jan 9, 1997 Issued
Array ( [id] => 3826909 [patent_doc_number] => 05832289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'System for estimating worst time duration required to execute procedure calls and looking ahead/preparing for the next stack operation of the forthcoming procedure calls' [patent_app_type] => 1 [patent_app_number] => 8/781213 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 17190 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832289.pdf [firstpage_image] =>[orig_patent_app_number] => 781213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781213
System for estimating worst time duration required to execute procedure calls and looking ahead/preparing for the next stack operation of the forthcoming procedure calls Jan 9, 1997 Issued
Array ( [id] => 3895173 [patent_doc_number] => 05765009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Barrier synchronization system in parallel data processing' [patent_app_type] => 1 [patent_app_number] => 8/779493 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 12669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765009.pdf [firstpage_image] =>[orig_patent_app_number] => 779493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779493
Barrier synchronization system in parallel data processing Jan 7, 1997 Issued
08/753255 HIGH SPEED NETWORK INTERFACE HAVING SAR PLUS PHYSICAL INTERFACE Nov 20, 1996 Abandoned
Array ( [id] => 3662272 [patent_doc_number] => 05684958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'System for preventing cell dropout on the transmitting side using timing signal and read completion signal to control the retransmission of previous cell' [patent_app_type] => 1 [patent_app_number] => 8/726544 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684958.pdf [firstpage_image] =>[orig_patent_app_number] => 726544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/726544
System for preventing cell dropout on the transmitting side using timing signal and read completion signal to control the retransmission of previous cell Oct 6, 1996 Issued
Array ( [id] => 3759498 [patent_doc_number] => 05754879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Integrated circuit for external bus interface having programmable mode select by selectively bonding one of the bond pads to a reset terminal via a conductive wire' [patent_app_type] => 1 [patent_app_number] => 8/717516 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5655 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754879.pdf [firstpage_image] =>[orig_patent_app_number] => 717516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717516
Integrated circuit for external bus interface having programmable mode select by selectively bonding one of the bond pads to a reset terminal via a conductive wire Sep 22, 1996 Issued
Array ( [id] => 3673912 [patent_doc_number] => 05649198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Mapping calculation units by dividing a calculation model which can be calculated in parallel on an application program' [patent_app_type] => 1 [patent_app_number] => 8/714527 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8116 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649198.pdf [firstpage_image] =>[orig_patent_app_number] => 714527 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714527
Mapping calculation units by dividing a calculation model which can be calculated in parallel on an application program Sep 15, 1996 Issued
Array ( [id] => 3837245 [patent_doc_number] => 05784291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods' [patent_app_type] => 1 [patent_app_number] => 8/705034 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 77 [patent_no_of_words] => 92671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784291.pdf [firstpage_image] =>[orig_patent_app_number] => 705034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705034
CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods Aug 28, 1996 Issued
Array ( [id] => 3829818 [patent_doc_number] => 05812797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Computer having a high density connector system' [patent_app_type] => 1 [patent_app_number] => 8/702195 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 17746 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812797.pdf [firstpage_image] =>[orig_patent_app_number] => 702195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702195
Computer having a high density connector system Aug 22, 1996 Issued
Array ( [id] => 3701261 [patent_doc_number] => 05644769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'System for optimizing program by virtually executing the instruction prior to actual execution of the program to invalidate unnecessary instructions' [patent_app_type] => 1 [patent_app_number] => 8/699220 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3695 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644769.pdf [firstpage_image] =>[orig_patent_app_number] => 699220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699220
System for optimizing program by virtually executing the instruction prior to actual execution of the program to invalidate unnecessary instructions Aug 18, 1996 Issued
Array ( [id] => 3736119 [patent_doc_number] => 05673425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'System for automatic generating instruction string to verify pipeline operations of a processor by inputting specification information having time for the processor to access hardware resources' [patent_app_type] => 1 [patent_app_number] => 8/698755 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 58 [patent_no_of_words] => 14277 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673425.pdf [firstpage_image] =>[orig_patent_app_number] => 698755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698755
System for automatic generating instruction string to verify pipeline operations of a processor by inputting specification information having time for the processor to access hardware resources Aug 15, 1996 Issued
Array ( [id] => 3634099 [patent_doc_number] => 05689661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems' [patent_app_type] => 1 [patent_app_number] => 8/683140 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5935 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689661.pdf [firstpage_image] =>[orig_patent_app_number] => 683140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683140
Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems Jul 17, 1996 Issued
Array ( [id] => 4232330 [patent_doc_number] => 06220768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Network asset survey tool for gathering data about node equipment' [patent_app_type] => 1 [patent_app_number] => 8/671107 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11087 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/220/06220768.pdf [firstpage_image] =>[orig_patent_app_number] => 671107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671107
Network asset survey tool for gathering data about node equipment Jun 27, 1996 Issued
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