Alejandro Valencia

Array ( [id] => 4402386 [patent_doc_number] => 06279094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for managing invalidation of virtual memory mapping table entries' [patent_app_type] => 1 [patent_app_number] => 9/137763 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279094.pdf [firstpage_image] =>[orig_patent_app_number] => 137763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255029 [patent_doc_number] => 06119204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization' [patent_app_type] => 1 [patent_app_number] => 9/108157 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6518 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119204.pdf [firstpage_image] =>[orig_patent_app_number] => 108157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269108 [patent_doc_number] => 06138211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'High-performance LRU memory capable of supporting multiple ports' [patent_app_type] => 1 [patent_app_number] => 9/107418 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138211.pdf [firstpage_image] =>[orig_patent_app_number] => 107418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4402346 [patent_doc_number] => 06279091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Program execution environment specification method and a recording medium containing the method recorded therein' [patent_app_type] => 1 [patent_app_number] => 9/057523 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7341 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279091.pdf [firstpage_image] =>[orig_patent_app_number] => 057523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310153 [patent_doc_number] => 06212603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory' [patent_app_type] => 1 [patent_app_number] => 9/057941 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7788 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212603.pdf [firstpage_image] =>[orig_patent_app_number] => 057941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206709 [patent_doc_number] => 06131146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Interleave memory control apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/056647 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4466 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131146.pdf [firstpage_image] =>[orig_patent_app_number] => 056647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422089 [patent_doc_number] => 06233650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Using FET switches for large memory arrays' [patent_app_type] => 1 [patent_app_number] => 9/053258 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233650.pdf [firstpage_image] =>[orig_patent_app_number] => 053258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176776 [patent_doc_number] => 06157991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method and apparatus for asynchronously updating a mirror of a source device' [patent_app_type] => 1 [patent_app_number] => 9/053420 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11808 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157991.pdf [firstpage_image] =>[orig_patent_app_number] => 053420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422518 [patent_doc_number] => 06272606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Automated job scheduling in a data storage and/or retrieval system' [patent_app_type] => 1 [patent_app_number] => 9/053566 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4933 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272606.pdf [firstpage_image] =>[orig_patent_app_number] => 053566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374565 [patent_doc_number] => 06170034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Hardware assisted mask read/write' [patent_app_type] => 1 [patent_app_number] => 9/052854 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3287 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170034.pdf [firstpage_image] =>[orig_patent_app_number] => 052854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424689 [patent_doc_number] => 06230231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Hash equation for MAC addresses that supports cache entry tagging and virtual address tables' [patent_app_type] => 1 [patent_app_number] => 9/044490 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3752 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230231.pdf [firstpage_image] =>[orig_patent_app_number] => 044490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152733 [patent_doc_number] => 06148386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Address generator circuity for a circular buffer' [patent_app_type] => 1 [patent_app_number] => 9/044529 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7350 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148386.pdf [firstpage_image] =>[orig_patent_app_number] => 044529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642392 [patent_doc_number] => 06430654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Apparatus and method for distributed non-blocking multi-level cache' [patent_app_type] => B1 [patent_app_number] => 09/010072 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10945 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430654.pdf [firstpage_image] =>[orig_patent_app_number] => 09010072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269185 [patent_doc_number] => 06138216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Microprocessor cache consistency' [patent_app_type] => 1 [patent_app_number] => 9/010256 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4143 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138216.pdf [firstpage_image] =>[orig_patent_app_number] => 010256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252542 [patent_doc_number] => 06076149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Programmable logic device using a two bit security scheme to prevent unauthorized access' [patent_app_type] => 1 [patent_app_number] => 9/009346 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4065 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076149.pdf [firstpage_image] =>[orig_patent_app_number] => 009346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4208107 [patent_doc_number] => 06154767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Methods and apparatus for using attribute transition probability models for pre-fetching resources' [patent_app_type] => 1 [patent_app_number] => 9/007898 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 45 [patent_no_of_words] => 22798 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154767.pdf [firstpage_image] =>[orig_patent_app_number] => 007898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4270141 [patent_doc_number] => 06223255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Microprocessor with an instruction level reconfigurable n-way cache' [patent_app_type] => 1 [patent_app_number] => 9/002955 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4598 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223255.pdf [firstpage_image] =>[orig_patent_app_number] => 002955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126794 [patent_doc_number] => 06058461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation' [patent_app_type] => 1 [patent_app_number] => 8/982588 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6622 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058461.pdf [firstpage_image] =>[orig_patent_app_number] => 982588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4088747 [patent_doc_number] => 06070231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method and apparatus for processing memory requests that require coherency transactions' [patent_app_type] => 1 [patent_app_number] => 8/982446 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11527 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070231.pdf [firstpage_image] =>[orig_patent_app_number] => 982446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179096 [patent_doc_number] => 06115787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Disc storage system having cache memory which stores compressed data' [patent_app_type] => 1 [patent_app_number] => 8/964458 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 13443 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115787.pdf [firstpage_image] =>[orig_patent_app_number] => 964458 [rel_patent_id] =>[rel_patent_doc_number] =>)