Search

Alejandro Valencia

Examiner (ID: 7553, Phone: (571)270-5473 , Office: P/2853 )

Most Active Art Unit
2853
Art Unit(s)
2853, 2861
Total Applications
1434
Issued Applications
552
Pending Applications
202
Abandoned Applications
678

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4151610 [patent_doc_number] => 06035367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Computer file system providing looped file structure for post-occurrence data collection of asynchronous events' [patent_app_type] => 1 [patent_app_number] => 8/835104 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5692 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035367.pdf [firstpage_image] =>[orig_patent_app_number] => 835104 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835104
Computer file system providing looped file structure for post-occurrence data collection of asynchronous events Apr 2, 1997 Issued
Array ( [id] => 4223739 [patent_doc_number] => 06078984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method of operating a control system which includes a nonvolatile memory unit having memory banks and a volatile memory unit' [patent_app_type] => 1 [patent_app_number] => 8/824789 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5318 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078984.pdf [firstpage_image] =>[orig_patent_app_number] => 824789 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824789
Method of operating a control system which includes a nonvolatile memory unit having memory banks and a volatile memory unit Mar 25, 1997 Issued
Array ( [id] => 4335129 [patent_doc_number] => 06243790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Methods and apparatus for re-arranging logical drives in a disk array apparatus' [patent_app_type] => 1 [patent_app_number] => 8/823755 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8458 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243790.pdf [firstpage_image] =>[orig_patent_app_number] => 823755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823755
Methods and apparatus for re-arranging logical drives in a disk array apparatus Mar 24, 1997 Issued
Array ( [id] => 3967312 [patent_doc_number] => 05983324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Data prefetch control method for main storage cache for protecting prefetched data from replacement before utilization thereof' [patent_app_type] => 1 [patent_app_number] => 8/823836 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10332 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983324.pdf [firstpage_image] =>[orig_patent_app_number] => 823836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823836
Data prefetch control method for main storage cache for protecting prefetched data from replacement before utilization thereof Mar 24, 1997 Issued
Array ( [id] => 4037449 [patent_doc_number] => 05883864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Media library having locally vectored drive addressing' [patent_app_type] => 1 [patent_app_number] => 8/804766 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6832 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883864.pdf [firstpage_image] =>[orig_patent_app_number] => 804766 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804766
Media library having locally vectored drive addressing Feb 23, 1997 Issued
Array ( [id] => 4059133 [patent_doc_number] => 05909704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'High speed address generator' [patent_app_type] => 1 [patent_app_number] => 8/702826 [patent_app_country] => US [patent_app_date] => 1997-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1989 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909704.pdf [firstpage_image] =>[orig_patent_app_number] => 702826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702826
High speed address generator Jan 8, 1997 Issued
Array ( [id] => 4052144 [patent_doc_number] => 05943682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Programmable control sequencer of disk controller and method for map allocation therefor' [patent_app_type] => 1 [patent_app_number] => 8/777142 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9191 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943682.pdf [firstpage_image] =>[orig_patent_app_number] => 777142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777142
Programmable control sequencer of disk controller and method for map allocation therefor Dec 29, 1996 Issued
Array ( [id] => 4373793 [patent_doc_number] => 06202135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'System and method for reconstructing data associated with protected storage volume stored in multiple modules of back-up mass data storage facility' [patent_app_type] => 1 [patent_app_number] => 8/774124 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 23279 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202135.pdf [firstpage_image] =>[orig_patent_app_number] => 774124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/774124
System and method for reconstructing data associated with protected storage volume stored in multiple modules of back-up mass data storage facility Dec 22, 1996 Issued
Array ( [id] => 3815752 [patent_doc_number] => 05829029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Private cache miss and access management in a multiprocessor system with shared memory' [patent_app_type] => 1 [patent_app_number] => 8/769682 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 69 [patent_no_of_words] => 13168 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 553 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829029.pdf [firstpage_image] =>[orig_patent_app_number] => 769682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769682
Private cache miss and access management in a multiprocessor system with shared memory Dec 17, 1996 Issued
Array ( [id] => 3969496 [patent_doc_number] => 05956752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method and apparatus for accessing a cache using index prediction' [patent_app_type] => 1 [patent_app_number] => 8/767082 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4338 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956752.pdf [firstpage_image] =>[orig_patent_app_number] => 767082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767082
Method and apparatus for accessing a cache using index prediction Dec 15, 1996 Issued
Array ( [id] => 4001715 [patent_doc_number] => 05950220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address space' [patent_app_type] => 1 [patent_app_number] => 8/766242 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4668 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950220.pdf [firstpage_image] =>[orig_patent_app_number] => 766242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766242
Method and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address space Dec 12, 1996 Issued
Array ( [id] => 4237251 [patent_doc_number] => 06112278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method to store initiator information for SCSI data transfer' [patent_app_type] => 1 [patent_app_number] => 8/723110 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2889 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112278.pdf [firstpage_image] =>[orig_patent_app_number] => 723110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723110
Method to store initiator information for SCSI data transfer Sep 29, 1996 Issued
08/720396 VIRTUAL ADDRESSING FOR SUBSYSTEM DMA Sep 29, 1996 Abandoned
Array ( [id] => 4021917 [patent_doc_number] => 05987567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'System and method for caching texture map information' [patent_app_type] => 1 [patent_app_number] => 8/723108 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 5955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987567.pdf [firstpage_image] =>[orig_patent_app_number] => 723108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723108
System and method for caching texture map information Sep 29, 1996 Issued
Array ( [id] => 4022154 [patent_doc_number] => 05987582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of obtaining a buffer contiguous memory and building a page table that is accessible by a peripheral graphics device' [patent_app_type] => 1 [patent_app_number] => 8/724566 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5316 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987582.pdf [firstpage_image] =>[orig_patent_app_number] => 724566 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724566
Method of obtaining a buffer contiguous memory and building a page table that is accessible by a peripheral graphics device Sep 29, 1996 Issued
08/718148 IMPROVED COMMUNICATIONS SYSTEMS APPARATUS AND METHODS USING A SINGLE CHIP MULTISPEED MULTIPORT NETWORK SWITCH Sep 17, 1996 Abandoned
Array ( [id] => 4018602 [patent_doc_number] => 05924127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Address translation buffer system and method for invalidating address translation buffer, the address translation buffer partitioned into zones according to a computer attribute' [patent_app_type] => 1 [patent_app_number] => 8/714395 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4054 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924127.pdf [firstpage_image] =>[orig_patent_app_number] => 714395 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714395
Address translation buffer system and method for invalidating address translation buffer, the address translation buffer partitioned into zones according to a computer attribute Sep 15, 1996 Issued
Array ( [id] => 4199167 [patent_doc_number] => 06038648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Semiconductor memory device having the same access timing over clock cycles' [patent_app_type] => 1 [patent_app_number] => 8/707386 [patent_app_country] => US [patent_app_date] => 1996-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9934 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 493 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038648.pdf [firstpage_image] =>[orig_patent_app_number] => 707386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707386
Semiconductor memory device having the same access timing over clock cycles Sep 3, 1996 Issued
08/697102 MULTIPROCESSOR OPERATION IN A MULTIMEDIA SIGNAL PROCESSOR Aug 18, 1996 Abandoned
08/696636 MICROCONTROLLER INCLUDING AN INTERNAL MEMORY UNIT AND CIRCUITRY TO GENERATE AN ASSOCIATED ENABLE SIGNAL Aug 13, 1996 Abandoned
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