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Alejandro Valencia

Examiner (ID: 7553, Phone: (571)270-5473 , Office: P/2853 )

Most Active Art Unit
2853
Art Unit(s)
2853, 2861
Total Applications
1434
Issued Applications
552
Pending Applications
202
Abandoned Applications
678

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4121338 [patent_doc_number] => 06023745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Scoreboarding for DRAM access within a multi-array DRAM device using simultaneous activate and read/write accesses' [patent_app_type] => 1 [patent_app_number] => 8/694646 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 14780 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023745.pdf [firstpage_image] =>[orig_patent_app_number] => 694646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694646
Scoreboarding for DRAM access within a multi-array DRAM device using simultaneous activate and read/write accesses Aug 7, 1996 Issued
Array ( [id] => 4033741 [patent_doc_number] => 05963980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Microprocessor-based memory card that limits memory accesses by application programs and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/663166 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4422 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963980.pdf [firstpage_image] =>[orig_patent_app_number] => 663166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663166
Microprocessor-based memory card that limits memory accesses by application programs and method of operation Jul 28, 1996 Issued
Array ( [id] => 3978252 [patent_doc_number] => 05937431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Multi- node, multi-level cache- only memory architecture with relaxed inclusion' [patent_app_type] => 1 [patent_app_number] => 8/679082 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7418 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937431.pdf [firstpage_image] =>[orig_patent_app_number] => 679082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679082
Multi- node, multi-level cache- only memory architecture with relaxed inclusion Jul 11, 1996 Issued
Array ( [id] => 4057322 [patent_doc_number] => 05996044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Sampling frequency converting device and memory address control device' [patent_app_type] => 1 [patent_app_number] => 8/677974 [patent_app_country] => US [patent_app_date] => 1996-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 14633 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996044.pdf [firstpage_image] =>[orig_patent_app_number] => 677974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677974
Sampling frequency converting device and memory address control device Jul 9, 1996 Issued
Array ( [id] => 3954799 [patent_doc_number] => 05900011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Integrated processor/memory device with victim data cache' [patent_app_type] => 1 [patent_app_number] => 8/675272 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9696 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900011.pdf [firstpage_image] =>[orig_patent_app_number] => 675272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675272
Integrated processor/memory device with victim data cache Jun 30, 1996 Issued
Array ( [id] => 3954680 [patent_doc_number] => 05873123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries' [patent_app_type] => 1 [patent_app_number] => 8/670116 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6043 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873123.pdf [firstpage_image] =>[orig_patent_app_number] => 670116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670116
Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries Jun 24, 1996 Issued
Array ( [id] => 4371231 [patent_doc_number] => 06216213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for compression, decompression, and execution of program code' [patent_app_type] => 1 [patent_app_number] => 8/660368 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4975 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216213.pdf [firstpage_image] =>[orig_patent_app_number] => 660368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660368
Method and apparatus for compression, decompression, and execution of program code Jun 6, 1996 Issued
Array ( [id] => 4025232 [patent_doc_number] => 06006313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Semiconductor memory device that allows for reconfiguration around defective zones in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/660738 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 14185 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006313.pdf [firstpage_image] =>[orig_patent_app_number] => 660738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660738
Semiconductor memory device that allows for reconfiguration around defective zones in a memory array Jun 5, 1996 Issued
Array ( [id] => 3955437 [patent_doc_number] => 05940870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Address translation for shared-memory multiprocessor clustering' [patent_app_type] => 1 [patent_app_number] => 8/651150 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940870.pdf [firstpage_image] =>[orig_patent_app_number] => 651150 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651150
Address translation for shared-memory multiprocessor clustering May 20, 1996 Issued
Array ( [id] => 4006984 [patent_doc_number] => 05960463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Cache controller with table walk logic tightly coupled to second level access logic' [patent_app_type] => 1 [patent_app_number] => 8/649847 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8536 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960463.pdf [firstpage_image] =>[orig_patent_app_number] => 649847 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649847
Cache controller with table walk logic tightly coupled to second level access logic May 15, 1996 Issued
Array ( [id] => 4011516 [patent_doc_number] => 05893152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory' [patent_app_type] => 1 [patent_app_number] => 8/612754 [patent_app_country] => US [patent_app_date] => 1996-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5113 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893152.pdf [firstpage_image] =>[orig_patent_app_number] => 612754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/612754
Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory Mar 7, 1996 Issued
Array ( [id] => 3893759 [patent_doc_number] => 05825991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'System for balancing CPU demands in a high-volume print server' [patent_app_type] => 1 [patent_app_number] => 8/550312 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5670 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825991.pdf [firstpage_image] =>[orig_patent_app_number] => 550312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550312
System for balancing CPU demands in a high-volume print server Oct 29, 1995 Issued
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