
Alexander A. Singh
Examiner (ID: 17626, Phone: (571)270-0243 , Office: P/2834 )
| Most Active Art Unit | 2834 |
| Art Unit(s) | 2834 |
| Total Applications | 761 |
| Issued Applications | 552 |
| Pending Applications | 77 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12936172
[patent_doc_number] => 09831288
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-28
[patent_title] => Integrated circuit cointegrating a FET transistor and a RRAM memory point
[patent_app_type] => utility
[patent_app_number] => 15/387850
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5217
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387850
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/387850 | Integrated circuit cointegrating a FET transistor and a RRAM memory point | Dec 21, 2016 | Issued |
Array
(
[id] => 12108840
[patent_doc_number] => 09865328
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-09
[patent_title] => 'Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system'
[patent_app_type] => utility
[patent_app_number] => 15/367968
[patent_app_country] => US
[patent_app_date] => 2016-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 11013
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367968
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/367968 | Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system | Dec 1, 2016 | Issued |
Array
(
[id] => 11760068
[patent_doc_number] => 20170206937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'HYBRID SYSTEM INTEGRATING PACKAGE-ON-PACKAGE SOC AND EMBEDDED MULTI-CHIP PACKAGE ON ONE MAIN CIRCUIT BOARD'
[patent_app_type] => utility
[patent_app_number] => 15/297170
[patent_app_country] => US
[patent_app_date] => 2016-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3294
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297170
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/297170 | HYBRID SYSTEM INTEGRATING PACKAGE-ON-PACKAGE SOC AND EMBEDDED MULTI-CHIP PACKAGE ON ONE MAIN CIRCUIT BOARD | Oct 18, 2016 | Abandoned |
Array
(
[id] => 11118639
[patent_doc_number] => 20160315614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'MEMORY MODULES'
[patent_app_type] => utility
[patent_app_number] => 15/202839
[patent_app_country] => US
[patent_app_date] => 2016-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9211
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202839
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/202839 | Memory modules including plural memory devices arranged in rows and module resistor units | Jul 5, 2016 | Issued |
Array
(
[id] => 11057077
[patent_doc_number] => 20160254039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-01
[patent_title] => 'MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/149989
[patent_app_country] => US
[patent_app_date] => 2016-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7350
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15149989
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/149989 | Memory device and memory system including the same | May 8, 2016 | Issued |
Array
(
[id] => 12088908
[patent_doc_number] => 09842640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-12
[patent_title] => 'Refresh control circuit and memory device including same'
[patent_app_type] => utility
[patent_app_number] => 15/093418
[patent_app_country] => US
[patent_app_date] => 2016-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6513
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093418
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/093418 | Refresh control circuit and memory device including same | Apr 6, 2016 | Issued |
Array
(
[id] => 11607797
[patent_doc_number] => 20170125100
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'PERIPHERAL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE AND/OR PERIPHERAL CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/091702
[patent_app_country] => US
[patent_app_date] => 2016-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 11308
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091702
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/091702 | Peripheral circuit, semiconductor memory device and operating method of the semiconductor device and/or peripheral circuit | Apr 5, 2016 | Issued |
Array
(
[id] => 11983402
[patent_doc_number] => 20170287557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'FILAMENT CONFINEMENT IN REVERSIBLE RESISTANCE-SWITCHING MEMORY ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 15/088902
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11648
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088902
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/088902 | Filament confinement in reversible resistance-switching memory elements | Mar 31, 2016 | Issued |
Array
(
[id] => 11983393
[patent_doc_number] => 20170287548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'APPARATUSES AND METHODS FOR REFRESH CONTROL'
[patent_app_type] => utility
[patent_app_number] => 15/089346
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5873
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089346
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089346 | Apparatuses and methods for refresh control | Mar 31, 2016 | Issued |
Array
(
[id] => 11071026
[patent_doc_number] => 20160267990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/055262
[patent_app_country] => US
[patent_app_date] => 2016-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8123
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055262
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/055262 | Semiconductor memory device that applies an initial pass voltage followed by a final pass voltage to non-selected word lines during a write operation | Feb 25, 2016 | Issued |
Array
(
[id] => 11353445
[patent_doc_number] => 20160372185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-22
[patent_title] => 'Methods of Operating Non-Volatile Memory Devices'
[patent_app_type] => utility
[patent_app_number] => 15/055186
[patent_app_country] => US
[patent_app_date] => 2016-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 13508
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055186
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/055186 | Methods of programming memory cells in non-volatile memory devices | Feb 25, 2016 | Issued |
Array
(
[id] => 11071007
[patent_doc_number] => 20160267971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/055284
[patent_app_country] => US
[patent_app_date] => 2016-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 14292
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055284
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/055284 | SEMICONDUCTOR MEMORY DEVICE | Feb 25, 2016 | Abandoned |
Array
(
[id] => 12334224
[patent_doc_number] => 09947408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-17
[patent_title] => Semiconductor memory device that applies same voltage to two adjacent word lines for access
[patent_app_type] => utility
[patent_app_number] => 15/055232
[patent_app_country] => US
[patent_app_date] => 2016-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 41
[patent_no_of_words] => 18677
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 388
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055232
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/055232 | Semiconductor memory device that applies same voltage to two adjacent word lines for access | Feb 25, 2016 | Issued |
Array
(
[id] => 10809354
[patent_doc_number] => 20160155513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-02
[patent_title] => 'PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS'
[patent_app_type] => utility
[patent_app_number] => 15/019397
[patent_app_country] => US
[patent_app_date] => 2016-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8500
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15019397
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/019397 | Program operations with embedded leak checks | Feb 8, 2016 | Issued |
Array
(
[id] => 10787153
[patent_doc_number] => 20160133309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'CIRCUITS AND METHODS FOR DQS AUTOGATING'
[patent_app_type] => utility
[patent_app_number] => 14/997268
[patent_app_country] => US
[patent_app_date] => 2016-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10564
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997268
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/997268 | Circuits and methods for DQS autogating | Jan 14, 2016 | Issued |
Array
(
[id] => 12102387
[patent_doc_number] => 09859490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-02
[patent_title] => 'Electronic device including a semiconductor memory having multi-layered structural free layer'
[patent_app_type] => utility
[patent_app_number] => 14/918356
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 10270
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918356
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/918356 | Electronic device including a semiconductor memory having multi-layered structural free layer | Oct 19, 2015 | Issued |
Array
(
[id] => 11787334
[patent_doc_number] => 09396789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-19
[patent_title] => 'Memory control device and a delay controller'
[patent_app_type] => utility
[patent_app_number] => 14/879925
[patent_app_country] => US
[patent_app_date] => 2015-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3207
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879925
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/879925 | Memory control device and a delay controller | Oct 8, 2015 | Issued |
Array
(
[id] => 10709761
[patent_doc_number] => 20160055909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'Integrated Circuit Comprising an Input Transistor Including a Charge Storage Structure'
[patent_app_type] => utility
[patent_app_number] => 14/828738
[patent_app_country] => US
[patent_app_date] => 2015-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5097
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828738
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/828738 | Integrated Circuit Comprising an Input Transistor Including a Charge Storage Structure | Aug 17, 2015 | Abandoned |
Array
(
[id] => 10703043
[patent_doc_number] => 20160049191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-18
[patent_title] => 'Integrated Circuit for Storing Data'
[patent_app_type] => utility
[patent_app_number] => 14/828364
[patent_app_country] => US
[patent_app_date] => 2015-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5611
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828364
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/828364 | Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories | Aug 16, 2015 | Issued |
Array
(
[id] => 11897944
[patent_doc_number] => 09767883
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'Semiconductor memory device that performs a refresh operation'
[patent_app_type] => utility
[patent_app_number] => 14/827686
[patent_app_country] => US
[patent_app_date] => 2015-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 6885
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827686
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/827686 | Semiconductor memory device that performs a refresh operation | Aug 16, 2015 | Issued |