Alexander Belousov

Array ( [id] => 12047409 [patent_doc_number] => 09825018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/473644 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 218 [patent_no_of_words] => 52273 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12040503 [patent_doc_number] => 09818738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/473647 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 52326 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11932636 [patent_doc_number] => 09799640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/473651 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 52181 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 475 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11817977 [patent_doc_number] => 09721937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/473537 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 52502 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11753478 [patent_doc_number] => 09711496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells' [patent_app_type] => utility [patent_app_number] => 15/473542 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 119 [patent_no_of_words] => 52515 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16013919 [patent_doc_number] => 20200181802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => THERMAL PROCESSING METHOD FOR SILICON WAFER [patent_app_type] => utility [patent_app_number] => 16/305680 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16305680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11917311 [patent_doc_number] => 09785496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens' [patent_app_type] => utility [patent_app_number] => 15/456482 [patent_app_country] => US [patent_app_date] => 2017-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 187 [patent_figures_cnt] => 282 [patent_no_of_words] => 44404 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11666199 [patent_doc_number] => 20170154918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'Back Side Illuminated Image Sensor with Reduced Sidewall-Induced Leakage' [patent_app_type] => utility [patent_app_number] => 15/431132 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11904333 [patent_doc_number] => 09773773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/395751 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11918456 [patent_doc_number] => 09786648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/395833 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11891011 [patent_doc_number] => 09761575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/395800 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11891009 [patent_doc_number] => 09761574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATECNT-short-configured, metal-short-configured, and AA-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/392712 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11862012 [patent_doc_number] => 09741703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/391884 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11911263 [patent_doc_number] => 09780083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, TS-short-configured, metal-short configured, and AA-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/392755 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11615584 [patent_doc_number] => 09653446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/390966 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12202482 [patent_doc_number] => 09905553 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/390862 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11599785 [patent_doc_number] => 09646961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-09 [patent_title] => 'Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells' [patent_app_type] => utility [patent_app_number] => 15/390912 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 219 [patent_no_of_words] => 51709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14812855 [patent_doc_number] => 20190273037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => VERTICAL BOND-WIRE STACKED CHIP-SCALE PACKAGE WITH APPLICATION-SPECIFIC INTEGRATED CIRCUIT DIE ON STACK, AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 16/349095 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16349095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13514429 [patent_doc_number] => 20180308757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/770258 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15770258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13984043 [patent_doc_number] => 20190061179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => EMERGENCY STOP PRESSURE SENSOR, SAFETY DEVICE, AND SAFETY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/080902 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16080902 [rel_patent_id] =>[rel_patent_doc_number] =>)